Sr PD Engineer

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs.

Qualcomm’s Connectivity SoC organization is seeking candidates for physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies. Tasks also involve the tiles level development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities in this role involves the experience of functional and test (DFT) mode constraints for place and route, floorplanning, power planning IR drop analysis routing, timing optimization and closure implementing timing fixes and functional ECOs debugging and fixing physical violations and formal verification. The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product. Required Skill/experience: 2+ years industry experience in the following areas Tiles level or sub-system level or SoC top level physical design successful tapeout experience Floorplanning of macro cells Place & Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion Compiler Timing closure (STA) experience in Synopsys PTSI Function ECO implementation Formal verification (FV) experience Power domain analysis (IR Drop/PDN) experience Physical verification (PV) experience Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  disability-accomodations@qualcomm.com  or call Qualcomm's toll-free number found  here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies :   Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for