Soc Engineer (synthesis/timing) -18607

Descriptions & Requirements

Job Description and Requirements

We’re looking for SOC engineers working on ASIC/SOC projects, at Synopsys Ho Chi Minh City, District 7. Responsibilities and Duties Synthesis LEC LDRC GCA STA PTPX Responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team. Contributes to both turnkey projects and as a trusted advisor to customer design. Develop innovative solutions to problems with little guidance and implement them independently. Set task-level goals and consistently meet schedules. Works with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

2 - 4 years of related experience. Good of ASIC/SOC design, synthesis, timing closure. Familiar with Synthesis, LEC, STA flow. It’s a plus if you have experience in low-power, high-performance design, advanced nodes under 12nm. Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous. Familiar with scripting languages, such as TCL, Perl, Python. Good English/communication skills and willingness to work with customer. BS or MS with an EE or related major

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.