Principal Post-Silicon Applications Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You are a senior technical expert who is called upon when PCIe 6.0 or 7.0 silicon exhibits unexpected behavior under critical timelines. Over the past decade, you have developed deep expertise in diagnosing complex issues that span analog signal integrity, digital protocol implementation, and system-level interoperability, often working with incomplete information and demanding schedules. Your knowledge of PCIe link training at 64 GT/s extends beyond theory into practical application. You understand where PAM4 encoding can obscure margining issues, where FLIT mode negotiation may encounter difficulties, and how subtle impedance discontinuities can compromise bring-up success. Your experience debugging customer systems has given you the ability to identify power delivery issues from oscilloscope measurements and recognize when firmware assumptions conflict with hardware implementation. Leading technical discussions with customer architects and internal design teams is a natural extension of your work because you have established credibility through consistent results and deep technical knowledge. You operate effectively without requiring exhaustive documentation, developing test plans, executing them, adapting as needed, and documenting findings to benefit future engineers. Traveling approximately twice annually to customer sites or internal laboratories is an expected aspect of the role, and you recognize that on-site presence often accelerates resolution significantly. At Synopsys, you will work with the most advanced SerDes IP in the industry, and your contributions will directly influence what our customers bring to market.

Provide senior-level technical support to customers during silicon bring-up and production phases for PCIe 6.0, PCIe 7.0, including on-site engagement when critical issues require direct technical presence Lead comprehensive root cause analysis for complex signal integrity, protocol compliance, and interoperability challenges across analog, digital, and system integration layers Utilize advanced laboratory instrumentation including high-bandwidth oscilloscopes, real-time spectrum analyzers, bit error rate testers, vector networkanalyzers, and protocol analyzers to perform precision measurements and isolate failure mechanisms at 64 GT/s and higher data rates Analyze and simulate Verilog/SystemVerilogRTL, collaborating with digital design and firmware teams to resolve issues involving PAM4 encoding, FLIT mode operation, and link training state machine behavior Drive technical engagements with customer engineering teams and system architects, translating technical findings into clear recommendations and design guidance Develop and refine test methodologies, debug procedures, and technical best practices for next-generation SerDes validation and customer deployment Travel approximately twice per year to customer locations or internal development sites for critical bring-up support and technical collaboration The Impact You Will Have Enable customer tape-outs and production ramps by resolving technical blockers that would otherwise delay significant development programs Establish Synopsys as a recognized technical authority in PCIe 6.0/7.0 through substantive customer partnerships and effective technical problem resolution Provide real-world silicon and system-level insightstoIP design, validation, and product development teams, improving quality and reducing time-to-market for future releases