SoC Power Design Engineer (Engineer - Staff Eng)

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Qualcomm's Global SoC Power team is currently seeking candidate whose primary role is to implement and validate low power design intent requirements at the SoC-level.  The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development.  The role also expands to power analysis and projection of SoC Use Case power this may include creating power models and power dashboard for SoC level power targets.  The candidate will have the opportunity to work with IP designers, power target (Chipset/SW) teams, and Post-Silicon test teams to jointly ensure power intent design requirements and power projections are fully validated from pre-silicon to silicon and post-silicon power optimization.. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Bachelor's degree in Electrical or Computer Engineering plus: ASIC frontend development Logic design, RTL coding, verification, synthesis, and timing closure Hardware description languages (Verilog, VHDL, System Verilog) Power-aware implementation flow, including UPF/CPF/Conformal Low Power Check Scripting - Perl/Tcl/Python   PREFERRED QUALIFICATIONS: Master's degree in Electrical or Computer Engineering Experience with/in: Familiarity of overall SoC Infrastructure – DDR, Busses, CPUs, I/Os and DFT Components Familiarity of power islands, power gating, power sequencing and multi-voltage domain design Power analysis familiarity in areas of clocktree, peak power, TDP, limits management   Responsibilities/Duties: Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent design at SoC level Generate and validate power intent design (UPF) at SoC level  Review designs and guide IP designers' power intent design ensuring it meets SoC level low power implementation requirements Work with design verification in validating low power design featurs at SoC and IP level. Collaborate with company CAD and vendor to enhance existing power flows and tools Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent QA Execute power-aware implementation flow, including UPF/CPF/Conformal Low Power Check Review IP design's power features and power budgets/estimates Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone Perform power analysis/projection of SoC baseline power and deliver SoC power models to chipset Execute power simulation/analysis -- (PtPx/PowerArtist/Prime Power/PowerPro)   Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail