Chief Engineer & Architect, MRAM

242,900.00-323,800.00 Business Function: R&D Engineering Work Location: San Jose Great Oaks Headquarters--LOC_WDT_USCA23 Company Description WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide. This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today. We’re looking for people who want to build, solve, and operate at that level. Join us and let’s shape the future of data.

This role is the most senior technical individual contributor in memory design. Owns end-to-end product architecture from concept through silicon qualification, arbitrates the power/performance/area trade-offs that set competitiveness, and is the final technical authority across design, process and product engineering. Define the memory subsystem architecture (array, periphery, I/O, redundancy, test, reliability) and turn product requirements into a design spec Drive floorplan and physical architecture: array efficiency, periphery partitioning, power delivery, die-level signal integrity Own the multi-generation roadmap: node migration, density and performance scaling Decide cross-functional trade-offs across process integration, circuits, DFT, packaging and controller/firmware interfaces Own design methodology and EDA/CAD strategy: tools, flows, vendors, licenses Mentor senior and principal engineers through architecture and design reviews Represent the architecture to executives, customers, foundry partners and standards bodies Qualifications Required MS/PhD in EE, CE or related field 15+ years in memory or mixed-signal IC development; 5+ as architect or chief engineer 2+ memory products owned from architecture through production silicon Deep advanced CMOS FinFET expertise: layout, variability, reliability, DFM Memory architecture breadth (DRAM, NAND/NOR, SRAM, emerging NVM), depth in one Modern Cadence/Synopsys custom and digital flows through full-chip sign-off Owned EDA/CAD strategy; led multi-site programs through influence Preferred Embedded memory IP integration into SoCs; memory-controller co-design Foundry engagement on PDKs, test chips and DTCO Emerging NVM architecture; JEDEC, patents or publications Additional Information WD is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the " Know Your Rights: Workplace Discrimination is Illegal ” poster. Our pay transparency