Senior Engineer -Performance Verification

About this opportunity 
 We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe. As an Performance Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security. You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon. What you will do 
 We are looking for people who can do ASIC Top level verification with special focus on Performance Verification. Your responsibilities will include : Perform RTL performance analysis , analyze throughput, latency, bandwidth, QoS, cache efficiency and memory utilization Implement performance verification plans at SoC-level and performance debug using both simulation and emulation environments. Collaborate with architecture, design, software and verification teams to define performance requirements and ensure alignment with overall system goals Analyze and optimize system performance, including DDR, CPU, Interconnects and high-speed interface like PCIe, UCIe etc Understanding of cache coherency, memory hierarchy, DDR, NoC, and interconnect architectures Experience with high-speed protocols such as PCIe, Ethernet, AXI or DDR Experience with performance simulation tools Leverage AI-based tools and automation to improve engineering productivity and performance analysis workflows Role in the Team: Participate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier. Debug RTL designs/Testcases with help of EDA simulation tools, HW emulator and SW debuggers. Contribute to keeping tests clean in the CI regren running on all platformsssio. Develop of tests involving UVM VIPs (used in some of our tests) Do formal connectivity verification and gate level simulation (GLS) to compile the ASIC designs to run in HW emulators, like Siemens Veloce and Cadence Palladium interested in scripting and in developing and maintaining the TLV CI flow in projects, including visualization of results. You will bring 
 General skills you must possess: Solid C programming skills targeting ASICs or other type of embedded software programming. Solid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs. Desired knowledge and experience in: Using SW debuggers, waveforms windows etc. for HW/SW co-debugging of C-code running in the ASIC. Experience of multi core designs is a plus. GLS Coresight and other JTAG TAP related features Compiling designs for HW emulation Formal connectivity verification High speed interfaces like Ethernet, PCIe, CPRI ARM CPUs/cores, SMMU AMBA interconnect, preferably using Cadence STG or IWB Bonus knowledge and experiences are: XPROP GLS with timing, Power aware GLS Debugging tests running on HW Emulators and or Silicon Simulating and debugging tests running on SystemC/TLM platforms. Power aware verification (digital, not mixed signal) Using Formal tools for power verification Lab experience suitable for bring-up of ASIC Silicon prototypes . 
 “All academic credentials must be from recognized and accredited institutions and are further subject to verification.” Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft