SOC Engineering, Senior Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent the last few years deep in RTL code, turning specifications into working digital logic that actually synthesizes and meets timing. Good design is not just about functionality for you. It is about creating clean, robust RTL that enables efficient verification and predictable implementation. You know the difference between a state machine that looks clever and one that closes timing in silicon, and you care about that difference. Reading a micro-architecture spec comes naturally. You identify ambiguities, ask the right clarifying questions, and write Verilog or SystemVerilog RTL that reflects the intended design. Protocols like AXI, APB, and AHB are not mysteries to you. They are tools you have used and debugged. You have run lint checks, fixed CDC violations, and worked through synthesis reports enough times to spot the warning that actually matters. Working across time zones does not faze you. You write clear emails, show up prepared to design reviews, and know when to escalate a question versus when to make a call and move forward. At Synopsys, you will work on real SoC designs for customers building everything from automotive systems to high-performance compute, and what you design will go to silicon.

Write and review Verilog, SystemVerilog, or VHDL RTL for block-level designs including state machines, pipelines, FIFOs, and memory controllers based on micro-architecture specifications Run RTL quality checks using tools like linting, CDC/RDC analysis, and synthesis to ensure your design is clean before handoff to physical design Collaborate with verification engineers to debug testbench failures, refine corner cases, and close coverage gaps Work with physical design teams to resolve timing issues, optimize logic for synthesis, and support timing closure from netlist through signoff Implement standard interface protocols including AXI, APB, AHB, I2C, and SPI within SoC subsystems Use scripting in Python, Tcl, or shell to automate repetitive tasks in the design flow and improve team productivity Participate in design reviews with cross-functional teams across the globe, clearly communicating design decisions and tradeoffs The Impact You Will Have Contribute RTL blocks that achieve timing, area, and power targets while minimizing design iterations Deliver full SoC designs that ship in products for automotive, aerospace, defense, and high-performance computing customers Improve design quality and reduce downstream debug time by catching issues early through disciplined use of lint, CDC, and synthesis checks Enable faster project ramp by writing clear design documentation and participating in knowledge transfer across global teams Help refine internal design flows and methodologies by identifying bottlenecks and proposing automation or process improvements Support customer-specific design requirements by translating high-level specs into implementable RTL that meets project constraints Build reusable IP blocks and design patterns that accelerate future projects across the Solutions group What You'll Need Bachelor's or Master's degree in Electrical Engineering or Computer Engineering 3 to 4 years of hands-on experience in ASIC or FPGA RTL design, implementation, and debug Strong proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines, memories, and FIFOs Working knowledge of the ASIC design flow from micro-architecture through RTL development, synthesis, and