Senior ASIC RTL Design Engineer, AI Networking IP

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We are looking for a talented ASIC RTL Design Engineer to join our IP design team developing high-performance networking and communications IP for advanced AMD products. Our intellectual property (IP) design team creates IP cores for use in high performance AMD products. Our designers work on industry-leading technologies for AI networking and communications. Your expertise will be deployed in ASIC projects targeting networking, security, storage, and other applications.          THE PERSON:     You are very proficient in Verilog RTL coding, and front-end design flows. You have experience with ASIC RTL design and front-end design processes, ideally including networking, communications, or other high-speed interface protocols. You have demonstrated your technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products.   You are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges.  You are a self-starter with a desire to learn and an ability to solve complex, novel, and non-recurring problems.  You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner .

Develop synthesizable RTL for IP cores targeting advanced technology nodes Utilize modern AI tools to achieve a high level of RTL design productivity through code generation, refactoring, documentation, and debug Collaborate directly with IP Architecture, IP Verification, and SoC integration teams Contribute to design specifications for IP cores Resolve IP simulation regression failures through close collaboration with the IP Verification Team and work with Verification Team members to ensure achievement of verification quality metrics Work with the SoC and Physical Design (PD) teams to meet Power/Performance/Area goals by providing synthesis and timing closure support Support the activities of the Emulation Team Coach and mentor less experienced designers Attend and contribute to regular technical status meetings       PREFERRED EXPERIENCE:     RTL (Verilog/SystemVerilog) design experience, preferably including ASIC implementations targeting leading-edge technologies Proven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure Experience driving AI-powered tools (VS Code, GitHub Copilot, Cursor) that integrate LLMs (Claude, Codex/GPT) for RTL design Experience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools Skilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Experience in modern, complex networking architecture and digital design in general Experience with networking or high-speed interface protocols such as Ethernet or PCIe, digital communication systems, or packet-processing applications  systems, optical communications, and packet processing applications Familiarity with