Design Engineer - Timing Methodology

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply.

Broadcom's Timing Sign-Off group in Central Engineering is looking for an energetic and self-driven professional to join our team. Our group’s mission is to provide advanced timing sign-off methodologies to Broadcom’s chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins. The candidate will participate and take ownership in Advanced Timing Sign-off methodology development and modeling for SOC and 3D/2.5D IC design. This includes complex studies and analysis of new concepts leading to design, development and improvement of existing and new solutions. The candidate should have experience in methodology development with deep knowledge of advanced silicon technologies, production testability and yield. The candidate should have Tapeout experience in high volume / high yield complex SOCs at advanced technology nodes. The candidate will be working closely with other experts across the company in a fast paced project oriented agile environment.  The candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time.

Develop and deploy timing signoff methodologies for advanced technology nodes. Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions. Participate & Lead in EDA flow development for Primetime, Tempus & Innovus. Qualifications : The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.   Strong hands-on experience in Timing Signoff methodology development and ownership. Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.  Strong hands-on experience with statistical data analysis and modeling. Strong hands-on experience in silicon technologies, testability and yield.  Strong hands-on experience with industry standard STA tools such as Primetime and Tempus. Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation. Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools. Strong analytical skills and extremely detail oriented, organized and methodical. Strong communication skills.  Clear and concise. Strong multitasking and context switching skills. Optimistic yet pragmatic attitude. Demonstrable skills for quick ramp-up. Ability to stay calm under extreme pressure.  Team player. Able to work with minimum supervision, handle ambiguity and drive problem solving to resolution autonomously.

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer.  We will