Staff Applications Engineer - Design Signoff

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in the semiconductor world, close enough to the metal to know that timing closure at 3nm is not a checkbox, it is a negotiation with physics. You have debugged power delivery networks that looked fine on paper but failed in silicon, and you learned early that the best solution is the one the customer can actually use on Monday morning. You are the kind of engineer who can walk into a room full of stressed design leads at a top foundry, look at their STA violations or EMIR hotspots, and know within ten minutes whether this is a tool issue, a methodology gap, or a design problem they have not named yet. You do not wait to be handed a perfect problem statement. You ask the right questions, triangulate fast, and move toward a solution even when half the data is missing. Working directly with customers energizes you. Not because you love travel or presentations, but because you care about making complex tools do what they are supposed to do in real design environments. You have a point of view on what good signoff looks like, and you are not afraid to push back when a flow does not make sense or a feature request misses the actual problem. At Synopsys, you will work with the teams building the tools and the customers depending on them to tape out. What you learn in Austin this week will shape what ships globally next quarter.

Deploy and support Synopsys signoff tools including PrimeTime , RedHawk-SC, PrimeClosure , PTECO, Tweaker, and StarRC at leading semiconductor companies and foundries working on advanced node SoCs and 3DICs Engage directly with customer design teams to diagnose and resolve static timing analysis, power integrity, signal integrity, and reliability signoff challenges across chip, package, and system levels Own technical issues end to end, working proactively with assigned accounts to deliver solutions that unblock tapeouts and keep development schedules on trac k Collaborate with Synopsys product development teams to translate customer pain points and feature requests into actionable product enhancements and roadmap priorities Support presales technical activities by demonstrating the Seascape platform and signoff solutions, helping sales teams articulate value and close opportunities Build and maintain a knowledge base of EDA best practices, deployment guides, and troubleshooting FAQs for use by both customers and internal support teams Participate in cross-functional initiatives within Synopsys, sharing what you learn in the field to improve tools, methodologies, and customer engagement strategies The Impact You Will Have Accelerate time to tapeout for customers by resolving complex STA, PDN, and reliability issues that would otherwise stall multi- million dollar design programs Shape the next generation of Synopsys signoff products by feeding real-world design challenges and customer requirements directly into engineering teams Expand adoption of the Seascape platform and advanced signoff flows across top-tier semiconductor companies, strengthening Synopsys' position in the signoff market Build deep technical trust with customer engineering teams, turning one-time