Memory Layout Design Engineer, Staff

Descriptions & Requirements

Job Description and Requirements

Memory Layout Design Engineer, Staff We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in the details of custom memory layout, and you know that the difference between a memory compiler that ships and one that stalls out is usually in how you handled density, matching, and DRC closure three weeks before tape-out. You think in layers, in device symmetry, in parasitic trade-offs. When a circuit designer hands you a schematic, you see not just what they drew but what they meant, and you know how to translate that intent into a layout that works across process corners and actually manufactures. You do not wait for someone to tell you the DRC is broken. You catch it, you debug it, and you drive the fix. You have migrated designs across technology nodes and lived through the surprises that come with FinFET scaling. You can sit with a junior engineer and explain why their routing choice will create an antenna violation, and you can sit with a methodology team and push back when an automation script does not account for real layout constraints. At Synopsys, you will work on memory IP that powers chips across the industry. The work is technical, the problems are real, and what you design will ship.

Design and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools Drive technology node migrations for memory compilers, resolving layout and verification issues that emerge with new process rules Collaborate directly with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent are preserved Develop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices that improve team efficiency and design quality Review layouts created by junior engineers, provide technical guidance, and mentor on complex layout challenges Support customer-specific memory customization projects, working through optimization requests and delivering production-ready IP The Impact You Will Have Your layouts will directly enable memory IP that ships in high-volume semiconductor products across automotive, mobile, AI, and data center applications You will reduce design cycle time by improving layout automation and methodology, allowing the team to take on more projects with higher quality Your ability to close complex DRC and LVS issues independently will unblock project milestones and keep compiler development on schedule You will raise the technical bar for the team by mentoring junior designers and establishing layout standards that scale across technology nodes Your collaboration with circuit and CAD teams will surface layout-driven insights that influence architecture and tool development decisions You will help Synopsys deliver memory IP that meets the most demanding area, performance, power, and reliability requirements from leading semiconductor companies Your work on technology migrations will position the memory IP portfolio for next-generation nodes and maintain Synopsys leadership in the market What You'll Need Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field 8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development Strong proficiency with custom layout tools such as