Principal Die-to-Die Interconnect Modeling Architect

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We are seeking a Modeling Architect to lead a technical team in building and evolving our foundational modeling platform for die-to-die (D2D) PHYs designs. This role focuses on communication theory, algorithm development, system-level modeling, performance prediction, adaptation algorithm modeling, and architectural verification The successful candidate will perform evaluation and tradeoff analysis using statistical tools over different signaling schemes (e.g., NZR vs. other), and analyze hardware architecture and implementation tradeoffs (equalization, error terms, noise budgets, etc.). Leading a technical team, the architect will drive algorithm verification of Verilog implementations, predictive adaptation algorithm run-time modeling, Monte Carlo evaluations of adaptation algorithms, and architectural verification with silicon correlation to achieve high model-to-silicon alignment. This role requires deep technical understanding of communication algorithms, timing and margin budgeting, equalization and error term analysis, and focus on cross-functional technical leadership.

System Modeling and Performance Prediction Develop comprehensive behavioral and architectural models that accurately predict complete link behavior before implementation. Build system-level models using MATLAB, Python, SystemC, or equivalent modeling environments. Model transmitter, receiver, package, channel, clocking, equalization, adaptation, and protocol interactions. Predict link performance including BER, latency, throughput, bandwidth density, power consumption, energy efficiency, and manufacturing margin. Perform architectural sensitivity analyses across process, voltage, temperature (PVT), aging, package variation, jitter, noise, and channel impairments. Apply communication theory to help develop robust, high-performance signaling architectures. Analyze equalization, timing recovery, clock recovery, calibration, and adaptive signal processing algorithms. Evaluate convergence behavior, numerical stability, hardware efficiency, and implementation feasibility. Guide algorithm development from mathematical concepts through production silicon implementation. Model deterministic and random timing uncertainties including jitter, skew, supply noise, process variation, and environmental effects. Establish margin methodologies that ensure robust operation across manufacturing and operating conditions. Collaborate with implementation teams to ensure timing assumptions are achievable in silicon. Architectural Verification and Silicon Correlation Define the architectural verification strategy to ensure system requirements are traceable from concept through production silicon. Develop behavioral reference models that serve as the golden standard for RTL implementation, verification, software development, and silicon validation. Establish architecture-level performance metrics, verification methodologies, and success criteria. Drive correlation between behavioral models, RTL simulation, laboratory characterization, and production silicon. Validate architectural assumptions through simulation and silicon measurements, identifying performance gaps and driving corrective actions. Develop verification methodologies that account for implementation effects including finite precision, analog non-idealities, and hardware constraints. Define comprehensive validation strategies covering nominal operation, corner cases, interoperability, and robustness across all operating conditions. Technical Leadership Provide technical leadership across architecture, analog, digital, firmware, packaging, signal integrity, verification, validation, and product engineering organizations. Lead architecture reviews and