HSIO Test Solutions Engineering Lead

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Marvell's Test Solutions Engineering (TSE) organization is seeking an experienced HSIO Test Solutions Engineering Lead to help define how next-generation silicon products are tested from architectural concept through high-volume manufacturing. TSE drives pre-silicon test strategy, DFT requirements, manufacturing test planning, and test chip validation. Partnering closely with Design, Validation, Product Engineering, and Test Engineering teams, TSE ensures products are architected for testability and equipped with the coverage, observability, and diagnostics required for successful product introduction, manufacturing ramp, and long-term quality. Working at the forefront of advanced SerDes, chiplet, die-to-die, and mixed-signal technologies, you'll help solve some of the industry's most challenging test and characterization problems while influencing products long before they reach production. What You Can Expect Required Qualifications BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Physics, or related field. 10+ years of experience in semiconductor Test Engineering, Product Engineering, DFT, Silicon Validation, or related disciplines. Strong understanding of semiconductor manufacturing, yield analysis, and qualification methodologies. Demonstrated ability to lead complex cross-functional technical initiatives. Experience in one or more of the following areas: High-speed SerDes technologies (56G, 112G, 224G and beyond) PCIe, CXL, UCIe, or die-to-die interfaces Design-for-Test (DFT) Silicon validation and debug Automated Test Equipment (ATE) Production test development Mixed-signal characterization and correlation Preferred Qualifications MS or PhD in Electrical Engineering, Computer Engineering, or related field. Experience with Advantest 93K and/or Teradyne UltraFLEX platforms. Experience with advanced packaging, chiplets, and heterogeneous integration technologies. Experience supporting AI, networking, cloud, or data center products. Python, automation, analytics, or test infrastructure development experience.

What You'll Do Define Test Strategy and DFT Architecture Develop test strategies and DFT requirements for advanced HSIO technologies. Influence product testability, observability, and diagnostics during architecture and design phases. Drive test planning and validation for next-generation SerDes, chiplet, and die-to-die architectures. Lead Test Chip and Silicon Validation Define and execute validation strategies for test chips and first-silicon bring-up. Characterize IP and subsystem functionality across voltage, frequency, and temperature conditions. Correlate validation results with manufacturing test requirements. Enable Manufacturing Readiness Develop production screening methodologies and manufacturing test plans. Collaborate with Product Engineering and Test Engineering teams to enable production deployment. Analyze production data and drive improvements in quality, yield, and test efficiency. Drive Technical Leadership Partner with Architecture, Design, DFT, Validation, Product Engineering, Reliability, and Manufacturing teams. Lead cross-functional reviews and influence key technical decisions. Mentor engineers and contribute to next-generation test methodologies and best practices. Expected Base Pay Range (USD) 138,400 - 204,800, $ per annum The successful candidate’s