Executive Director of R&D Engineering for 3DIC-Advance Packaging

General Information

Job Title

Executive Director of R&D Engineering for 3DIC-Advance Packaging

Job ID

17450

City

Sunnyvale

State/Province

California

Date Posted

11-May-2026

Job Category

Engineering

Job Subcategory

R&D Engineering

Hire Type

Employee

Remote Eligible

No

Base Salary Range: $268000 - $ 402000

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent the better part of two decades building semiconductor solutions that actually ship, not just pass design reviews, and you know that the hardest problems in 3DIC are never just technical. They live at the intersection of physics, economics, and customer reality. You understand that a chiplet architecture is only as good as the yield curve it produces and the system performance it enables, and you have made the tradeoffs enough times to know which ones matter. You lead organizations that span continents and disciplines, and you have learned that the difference between a team that delivers and one that stalls is usually clarity. Clarity of purpose, clarity of decision rights, clarity of what good looks like. You do not manage by deck, you manage by walking into a room, understanding the blocker, and removing it. You have credibility with customers because you have been in the room when a design did not work and you helped fix it. You have credibility with engineers because you still understand the signoff flow. You think in roadmaps, not features, and you know how to translate a market shift into a three-year technical plan that your team can actually execute. At Synopsys, you will shape the future of heterogeneous integration for AI and high-performance computing, and the team you build will define what is possible.

Lead the global engineering organization responsible for 3DIC silicon IP and advanced packaging design, covering layout, physical design, signal integrity, power integrity, thermal modeling, and mechanical stress analysis for AI infrastructure and HPC products Own the technical roadmap and execution strategy for chiplet architectures, heterogeneous integration, and die-to-die interconnect solutions that align with Synopsys business objectives and customer requirements Drive cross-functional collaboration with EDA tool development teams, product management, go-to-market, and customer success to ensure Synopsys 3DIC solutions are differentiated, adoptable, and production ready Engage directly with leading semiconductor customers and ecosystem partners to shape technical requirements, validate architectures, and accelerate adoption of Synopsys 3DIC and advanced packaging IP Build, scale, and mentor a high-performing, multi-site engineering team, establishing a culture of accountability, technical excellence, and continuous improvement Track and synthesize industry trends in 3DIC, chiplets, and advanced packaging, translating emerging technologies and competitive dynamics into actionable product and technology decisions Make sound engineering tradeoffs across performance, power, area, cost, yield, and manufacturability, ensuring solutions meet both technical and business success criteria The Impact You Will Have Define and deliver the silicon IP portfolio that enables Synopsys customers to build next-generation AI accelerators, data center processors, and high-performance compute systems using 3DIC and advanced packaging Shape the long-term technology roadmap for Synopsys in heterogeneous integration, influencing how the semiconductor industry approaches chiplet design,