Senior Post-Silicon Validation Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

About the Role We are looking for a hands-on Senior Post-Silicon Validation Engineer to own silicon bring-up, characterization, and system-level validation of complex mixed-signal SoCs, while enabling a smooth transition from validated silicon into product integration. You will define the validation strategy, build our test and validation capability from the ground up, and lead execution from first silicon through product readiness.

• Own post-silicon validation strategy, test planning, execution, coverage, and sign-off.

• Lead first silicon bring-up across power, clocks, debug interfaces, processor/memory subsystems, peripherals, and high-speed interfaces.

• Define and execute the validation strategy and readiness criteria needed to enable product integration, ensuring silicon, firmware, test infrastructure, and system interfaces are ready for integration.

• Own system-level test planning and execution, including functional, performance, stress, and corner-case testing.

• Help build the test and validation lab from the ground up, including equipment, infrastructure, test setups, and automated characterization and regression environments.

• Partner with RF/analog and mixed-signal designers on characterization of RF chains, PLLs, ADCs/DACs, clocking, and power.

• Work closely with systems/DSP teams to validate DSP and calibration algorithms on silicon and correlate measured performance with models and simulations.

• Partner with FPGA, firmware, RTL/DV, hardware, and systems teams to accelerate silicon bring-up, enable product integration, and drive end-to-end validation.<span