Lead Software Engineer - Logic Synthesis

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Description: Responsible for development and maintenance of the synthesizer for Palladium. Implementation for new VHDL/Verilog feature support in synthesizer. Logic optimization and performance improvement in synthesizer.

Requirement: This position requires a Bachelor or Master's degree in EE/CS/CE with 3-5 years of industry experience. Candidate should be proficient with C/C++, Operating system concepts. Design modeling using Verilog/SV, VHDL or SysC. Knowledge and experience in RTL modeling of BFMs along with exposure to verification methodologies using UVM and SC/TLM is preferable. EDA/CAD tool development experience or logic design verification experience is highly preferred. Knowledge and experience in AI tools like Copilot or Claude code is preferred. Requires good communication skills, attention to details, and ability to work in multi-site/multi-person project. We’re doing work that matters. Help us solve what others can’t.