ASIC Digital Design , Staff Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building RTL that ships in silicon, not just passes simulation. When you read a protocol specification, you see the corner cases that will break three months into verification, and you architect around them before anyone else notices. You are comfortable taking a huge page Ethernet spec and walking out with a micro-architecture that balances latency, power, and area without needing someone to hold your hand. You write Verilog that other engineers can actually read and maintain. Debugging asynchronous FIFO issues and CDC violations has taught you what good design discipline looks like, and you hold yourself to it even when schedules get tight. Multi-site collaboration does not slow you down. You can review someone's RTL in a different timezone, leave clear feedback, and move the design forward without waiting for a meeting. At Synopsys, you will work on IP cores that power everything from AI accelerators to automotive systems, and the designs you own will matter.

Design and code RTL for high-speed Ethernet IP cores ranging from 100G to 1.6T, focusing on low latency and timing closure in complex datapath and control logic Translate protocol specifications and functional requirements into micro-architecture and detailed design documents for DesignWare IP in Ethernet, AMBA AXI, CHI, PCIe, USB, MIPI, or memory controller domains Build and refine directed Verilog testbenches to improve functional and code coverage, analyzing metrics and defining targeted test cases that catch real bugs Perform technical reviews of functional specs, micro-architecture documents, and RTL code from peers across global design teams Drive timing analysis and closure for high-speed designs using synthesis, STA, lint, CDC, and formal verification flows Apply low power design methodologies and automotive safety requirements to IP development Collaborate with verification, integration, and product teams across Bangalore, the US, and other global sites to deliver production-quality IP on schedule The Impact You Will Have Your RTL will ship in customer SoCs powering data center infrastructure, automotive platforms, and AI systems used by millions of people The micro-architecture decisions you make today will determine whether a customer's chip meets their performance and power targets six months from now Your coverage improvements and directed tests will catch silicon bugs before tapeout, saving customers months of respins and lost revenue The design quality and documentation you deliver will set the standard for how the rest of the IP team approaches complex protocol implementations Your timing closure work on multi-gigabit interfaces will enable Synopsys to stay ahead in the race toward higher-speed Ethernet and interconnect IP The technical reviews you provide will level up junior engineers and prevent architectural mistakes from becoming costly late-stage fixes Your ability to work across sites will keep globally distributed projects on track and reduce friction in cross-functional handoffs What You'll Need Bachelor's in Electrical Engineering with 6+ years of hands-on ASIC or IP design experience, or Master's with 4+ years Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers Strong working knowledge of at least one protocol from this list: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI. High-speed Ethernet (100G and above) experience is a strong plus Proven ability