Design Verification Staff Engineer - 19165

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles Staff Verification Applications Engineer Senior Technical Applications Engineer, RTL Verification Staff Field Applications Engineer, Design Verification Technical Lead, Verification Solutions Staff Applications Engineer, Timing and Verification We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent a decade in the trenches of digital design, where timing exceptions are not theoretical exercises but the difference between a chip that tapes out and one that doesn't. You know what it looks like when a customer's constraint deck has 3,000 false paths and half of them are wrong, and you know how to walk them back from that edge without making them feel like they've been doing it wrong for years. You are comfortable sitting with a design team in Hsinchu on Tuesday debugging why their CDC violations won't converge, then jumping on a call with R&D in Mountain View on Wednesday to explain exactly what the tool needs to do differently. You translate between what the tool can do and what the customer actually needs, and you do it without losing either side. Methodology deployment is your craft. You have built flows that teams actually use, not ones that look good in a slide deck. You script in Tcl and Python because you have to, not because you love it, and you have debugged enough PrimeTime correlation issues to know that the problem is usually three layers deeper than where it first appears. At Synopsys, you will work with Taiwan's most strategic semiconductor accounts on verification and timing solutions that determine whether their next-generation SoCs actually work.

Lead full-cycle deployments of Timing Constraints Management (TCM), VC SpyGlass, and VCS across strategic accounts, from evaluation through production adoption and methodology integration Debug complex timing constraint issues including false path validation, multi-cycle path analysis, clock-domain crossing verification, and STA-to-simulation correlation problems in real customer designs Drive pilot projects that prove out constraint verification, RTL quality checking, and simulation-based timing validation flows in advanced-node SoC environments Build automation scripts and reusable deployment methodologies in Tcl, Python, and Perl that improve customer productivity and reduce time to signoff Deliver technical workshops and hands-on training on TCM constraint management, VC SpyGlass lint/CDC/RDC flows, and VCS simulation debug techniques Collaborate directly with R&D teams to escalate critical customer issues, validate new features, and shape product roadmaps based on what you see in the field Partner with sales and product management to identify technical expansion opportunities within accounts and translate customer pain points into business growth The Impact You Will Have Enable Taiwan semiconductor leaders to close timing on complex SoCs faster by deploying constraint verification methodologies that catch errors before they reach signoff Reduce customer debug cycles by building simulation and formal flows that correlate cleanly with static timing analysis, eliminating weeks of back-and-forth Drive adoption of VC SpyGlass across RTL verification teams, improving design quality and reducing CDC/RDC violations that would otherwise escape to silicon Shape how Synopsys verification tools evolve by feeding real customer use cases and methodology gaps directly back to product development Accelerate time-to-production for strategic accounts by creating reusable deployment