Design Verification Engineer

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The Data Accelerator (DACC) team at AMD is seeking an experienced Silicon Design Verification Engineer to take a significant role across multiple aspects of IP verification. This is an excellent opportunity to drive next generation technologies that are part of AMD’s products powering Servers, Datacenters, Client and Embedded markets. You will join one of the fastest-growing areas of adding custom hardware offload engines to support complex operations like encryption, authentication, compression, GPU/CPU compute offloads & virtual machines live migration. This is a tremendous opportunity to shape the rapidly expanding domain of custom hardware accelerators. The Design Verification (DV) group within this team is responsible for developing a scalable DV flow and environment with emphasis on automation (including AI-driven verification), power and performance verification (PPV) and emulation support. You will help define this strategy and mentor other engineers. Our management fosters continuous technical innovation and career development.   THE PERSON: Highly skilled in advanced ASIC Functional Verification techniques and planning, with a track record of owning complex verification challenges independently. Passionate about mentoring junior engineers, exploring new designs and implementation techniques and driving improvements to team methodology. The candidate enjoys an environment where everyone in the team can grow and develop with a sense of global team spirit. Strong analytical thinking and problem-solving skills, excellent attention to detail, and comfort operating with significant autonomy.

Architect, develop, and maintain block- and subsystem-level IP verification testbenches, test methodology and infrastructure, setting technical direction for the team Own detailed test plans for covering new features across multiple blocks and drive test plan reviews with cross-functional stakeholders Lead triage of regressions, debug complex simulations, analyze coverage, and drive resolution of technical issues with design, verification and other teams to achieve verification closure Deploy and help evolve industry leading verification methodologies such as UVM, formal verification, and AI-assisted verification flows Take end to end ownership of key features across multiple projects, and mentor junior and mid-level engineers on verification best practices Reproduce silicon functional bugs in simulations and/or formal verification tools Conduct code reviews and help establish coding and verification standards for the team   PREFERRED EXPERIENCE:   Extensive hands-on hardware verification experience (typically 8+ years) across multiple projects or tapeouts Proficient in Verilog, System Verilog, UVM and working in Linux and Windows environments Experience applying AI agents and skills to functional verification, and evaluating new AI-based verification tools for team-wide adoption Excellent programming skills Familiarity with Makefiles, scripting languages like perl, python, ruby etc.   HIGHLY DESIREABLE EXPERIENCE – AI/ML FOR VERIFICATION: Experience building or driving adoption of AI-assisted or agentic verification flows (e.g., LLM-generated UVM sequences/assertions, AI-assisted debug and log triage, automated root-cause analysis) Track record of applying machine learning or data-driven techniques to coverage closure,