Sr Manager - Physical Design

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You are an experienced and highly motivated ASIC Physical Design Engineer with over 5 years of relevant experience, you have honed your skills in state-of-the-art CAD tools and technologies, specifically ICC2/FC, ICV, and FinFet. Your excellent communication skills, both verbal and written, enable you to effectively collaborate with internal and external teams. You possess a strong desire to learn and explore new technologies, demonstrating excellent exploration and problem-solving skills. You are autonomous in your work, often guiding junior peers, and you bring innovative solutions to complex project challenges. At Synopsys, you will lead the physical design work for UCIe PHYs and testchips that define how chips connect in the next generation of systems.

Lead the physical design implementation of UCIe PHYs and testchips across advanced process nodes including 5nm and below Own synthesis, place and route, timing closure, physical verification, DFT, and ATPG workflows using tools like DC, PT, ICC2/FC, and ICV Manage and mentor a team of physical design engineers, balancing technical guidance with project execution and delivery accountability Drive cross-functional collaboration with verification, DFT, IP integration, and customer engineering teams to meet PPA and schedule commitments Represent the physical design team in customer engagements, translating technical constraints into actionable solutions and managing escalations Champion the adoption of new flows, tools, and methodologies that improve team productivity and product quality Provide regular project status updates to leadership, surfacing risks early and proposing mitigation strategies The Impact You Will Have Deliver production-quality UCIe PHY designs that enable next-generation chip-to-chip connectivity for Synopsys customers Improve design cycle time and PPA outcomes by driving tooling and methodology improvements across the physical design flow Build and scale a high-performing physical design team capable of handling multiple concurrent tapeouts in leading-edge technologies Strengthen customer confidence in Synopsys IP through on-time, high-quality silicon delivery and responsive technical engagement Influence product roadmap decisions by surfacing design insights and PPA tradeoffs that matter to end customers Mentor engineers who go on to lead their own projects, raising the technical bar across the organization Shape how Synopsys approaches physical design for advanced nodes by piloting new flows and feeding lessons learned back into the methodology team What You'll Need 13+ years of hands-on experience in ASIC physical design, with demonstrated expertise in synthesis, place and route, timing closure, and physical verification Multiple tapeouts and sign-offs in 5nm or more advanced process nodes Proficiency with industry-standard tools including DC, PT, ICC2/FC, and ICV Experience leading physical design teams independently, managing project timelines, and coordinating with cross-functional groups Proven track record working on SoC or IP tapeouts, handling multiple teams, and interfacing with customers or internal stakeholders Strong understanding of FinFET technology and the physical design challenges specific to advanced nodes Experience representing engineering in business unit or company-wide initiatives Who You Are You can walk into a room where timing is failing by 200ps and walk out with a concrete plan that your team believes in and