ASIC / FPGA Design Verification Engineer – (Lead or Senior)

ASIC / FPGA Design Verification Engineer – (Lead or Senior) Company: Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/ FPGA Design Verification Engineers – (Lead or Senior) to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products in El Segundo or Huntington Beach, CA.   Mission Develop scalable technical leaders who combine strong verification fundamentals, fluent UVM capability, technical ownership, systems awareness, mentorship, and increasing responsibility for verification execution, environments, closure activities, and team success. Level Intent Level IV engineers independently own verification scope, establish verification environments and infrastructure, mentor engineers, support closure leadership activities, and lead technical efforts when required. Level V engineers expand into broader subsystem ownership, larger technical coordination responsibilities, verification strategy influence, and leadership of verification efforts across complex programs.

Engineers support ASIC, FPGA, and SoC verification activities across advanced aerospace programs including space systems, satellite technologies, NASA mission support, Space Launch System (SLS) technologies, aviation platforms, communications systems, autonomous systems, and related digital subsystems. Candidates are expected to possess strong verification fundamentals and fluent UVM capability. Engineers should be prepared to discuss simulation concepts, debug methods, coverage approaches, requirements traceability, reusable verification infrastructure, UVC development, closure methodology, and broader verification strategy concepts during interviews. Why Join Us This organization supports a broad portfolio of aerospace and defense programs across ASICs, SoCs, and FPGAs, creating opportunities to contribute across multiple products, technologies, and technical domains over time. Teams combine complementary technical strengths and adapt responsibilities based on program needs, enabling engineers to deepen expertise while broadening systems understanding, mentorship capability, verification ownership, and technical leadership. The department intentionally develops scalable technical leaders and provides multiple paths for long‑term growth. Behavioral Expectations Engineers operate with ownership appropriate to level while contributing to planning, execution, integration, closure, mentoring, and continuous improvement activities. Candidates communicate status, risks, dependencies, technical concerns, and schedule impacts proactively while supporting broader team capability. Engineers are expected to support peer growth, develop broader systems awareness beyond immediate FPGA or ASIC boundaries, and help strengthen verification capability across programs.

Engineers independently own verification scope and contribute throughout product development by supporting verification planning, requirements traceability, simulation, integration, debug, closure, and delivery activities. Verification ownership includes accountability for verification execution, completeness, and closure. It does not imply primary ownership of architecture development, RTL implementation, or subsystem engineering responsibilities. Level IV and V engineers are expected to independently establish and expand SystemVerilog and UVM environments, reusable verification infrastructure, and UVC development activities with minimal support while guiding broader verification execution. Engineers are expected to define verification objectives, support measurable closure criteria, perform verification completeness assessments, and apply metrics‑driven approaches using coverage results, requirements traceability, bug trends, and risk assessments appropriate to role level. Responsibilities include system‑level troubleshooting across RTL, testbench, firmware/software, integration, and specification