Senior Power Management IP Verification & Validation Engineer

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

The VLSI Power Engineer role at SambaNova Systems requires a Master's or Ph.D. degree along with 7+ years of experience in verification and post-silicon validation for hardware accelerators. The ideal candidate has a solid grasp of computer architecture fundamentals to understand the intricacies of the Reconfigurable Dataflow Unit (RDU) architecture, since this role owns verification of the power management system that is tightly coupled to the RDU across both pre-silicon and post-silicon stages. The engineer will be responsible for delivering a bug-free design in close collaboration with RTL design teams, applying industry-standard verification methodologies such as UVM and SVA. Beyond pre-silicon work, the role extends into silicon bring-up, validation, and testing. Candidates should bring strong proficiency in SystemVerilog, along with working proficiency in C/C++, Python, and shell scripting to build and maintain verification flows and tooling.

• Define and plan pre-silicon verification strategy during the early stages of the project

• Execute pre-silicon verification of Power IPs, driving toward high functional and code coverage targets

• Following chip arrival, lead functional and system-level validation efforts of Power IPs to support low-power, high-performance rack system delivery

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Architecture

• 7+ years of experience in verification and post-silicon validation for hardware accelerators

• Hands-on experience with UVM and SVA in a SystemVerilog verification environment

• Hands-on experience with hardware validation, debugging, and testing

• Strong cross-functional collaboration and technical communication skills to effectively bridge RTL design and pre-silicon verification/post-silicon validation teams

• Domain knowledge of power management, RDU architecture, and computer architecture fundamentals

• Experience leveraging modern AI tools and AI-assisted workflows (e.g., for Python/Bash scripting) to automate flows, boost productivity, and streamline simulation post-processing

Base Pay Range

$250,000—$350,000 USD

Submission Guidelines Please note that in order to be considered an applicant for any