SoC Physical Design Engineer (Senior to Principal)

Company: Qualcomm Vietnam Company Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.     As a Qualcomm HW SoC Engineer, you will define, model, design (digital and/or analog), optimize , verify, validate , implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.   We are seeking a seasoned Staff / Sr Staff Physical Design Engineer to provide technical leadership across block-level, die-level and chip-level physical implementation on advanced FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

Bachelor's degree in Science , Engineering, or related field and 4 + years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.   OR   Master's degree in Science, Engineering, or related field and 3 + years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.   OR   PhD in Science, Engineering, or related field and 2 + years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.

Master's degree in VLSI , Electrical /Electronic Engineering, Physic Engineering, Computer Engineering, or Computer Science with 3 + years of experience .   Deep expertise in full chip and block level floor - planning , design implementation through place and route , ECO , STA, LEC / Timing / Power closure , and P hysical Verification ;   Experience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF)   Advanced Shell, Python and T cl scripting : ability to architect large-scale SOC back-end automation frameworks and flow infrastructure   Demonstrated experience or vision for applying Agentic AI methodologies to EDA challenges : autonomous agents, AI-driven optimization, LLM-assisted debugging   Strong communication skills : ability to present methodology decisions, risk assessments, and tape out readiness to senior management     Principal Duties & Responsibilities:   Leverages advanced ASIC knowledge and experience to define, model, design (digital , analog and/or mix signal ), op timize, ve rify, va lidat e and i mplemen t IP (block/SoC) development for a variety of high performance, high quality, low power products.   Participates in or leads the design implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.   Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.   Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.   Utilizes tools/applications (e.g., RTL to GDS Flow) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.   Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.     Level of Responsibility:   Works independently with minimal supervision.   Provides supervision/guidance to other team members.   Decision-making is significant in nature and affects work beyond immediate work group .   Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact,