Substrate Design Engineer

Meet the Team The System Hardware team in the Cisco Silicon One Optical Group is seeking an ASIC Package Design Engineer focused on advanced package and PCB design. As a member of the hardware design team, you will help develop the next generation of Cisco optical products, participating in the definition and design of current and future ASICs, packages, PCBs, and PCBAs. You will work with a team of electrical, mechanical, and thermal engineers, collaborating closely with system architects, ASIC engineers, and SI/PI engineers to create next-generation optical engines.

In this role, you will contribute to the development of advanced substrate and ASIC package layouts from early planning and floor planning through implementation, verification, and tape out. You will collaborate closely with system, hardware, SI/PI, silicon, thermal, mechanical, and manufacturing teams to deliver high-speed, robust, and manufacturable package solutions. This role requires strong hands-on experience with Cadence Allegro Package Designer and Cadence SiP Layout, along with a solid understanding of substrate technologies, HDI design, stack-ups, routing constraints, controlled impedance, power/ground distribution, and advanced multi-die integration. Responsibilities • Create and maintain advanced substrate layouts for BGA, flip-chip, SiP, and multi-die package designs, as well as HDI and mSAP PCB designs. • Perform substrate floor planning, bump/ball map implementation, pinout optimization, stack-up implementation, and routing planning. • Use Cadence Allegro Package Designer and Cadence SiP Layout for package substrate layout, routing, rule checking, and design release. • Implement routing for high-speed signals, differential pairs, power, and ground networks while meeting SI/PI, impedance, spacing, via, and manufacturing constraints. • Set up, review, and resolve package-level design rules, DRC violations, and manufacturability issues. • Review DFM/DFT requirements and support fabrication, assembly, tape out, and package bring-up activities. • Generate and maintain design release documentation, layout databases, and manufacturing output files. • Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, cost, and schedule. • Assist in developing and improving substrate/package layout methodologies, flows, design rules, and best practices. Minimum Qualifications • Bachelor’s degree with 5+ years of experience or Master’s degree with 3+ years of experience in Electrical Engineering, Packaging Engineering, or a related field. • Hands-on experience with Cadence Allegro Package Designer and Cadence SiP Layout. • Understanding of package substrate technologies, layer stack-ups, routing constraints, via structures, power/ground distribution, and controlled impedance. • Experience routing high-speed signals, differential pairs, power, and ground networks. • Experience with design rule setup, DRC resolution, layout verification, and design release for fabrication and assembly. • Understanding of substrate manufacturing processes, DFM requirements, and assembly constraints. Preferred Qualifications • Master’s degree in electrical engineering or a related field with 5+ years of experience. • Self-motivation, collaboration, strong communication, and a desire to innovate. • Strong attention to detail, ownership mindset, and ability to deliver manufacturable layouts on schedule. • Multi-year design experience with advanced package substrates, organic substrates, interposers, multi-chip modules, high-performance ASIC packages, and multi-die packaging technologies such as flip-chip, 2.5D, and 3D stacking. • Proficiency with Cadence Allegro platform tools, including PCB Editor, Advanced Package Designer, and SiP Layout. • Basic understanding of SI/PI tools such as XtractIM, PowerSI, HFSS, or similar tools. • Knowledge of