Senior Analog Layout Engineer

Lumai is redefining how the world computes. We are an ambitious, venture-backed UK startup pioneering a breakthrough AI accelerator for data centres which uses 3D optical compute. Our radical technology uses light to perform computation at orders of magnitude faster speeds and at far greater scales than ever before, all whilst consuming far less energy than traditional approaches. Lumai is unlocking performance and efficiency gains that could transform the economics of AI and compute infrastructure and reshape how intelligence scales globally. If you are passionate about bringing groundbreaking technology to market, and want to be part of a team pushing the boundaries of what is physically possible, Lumai is where you can make it happen. ABOUT LUMAI Founded in 2022, Lumai is a University of Oxford spinout using optical processing to accelerate large language models (LLMs) and other transformer-based AI systems. The team combines expertise in optical computing, machine learning, and physics. Lumai has already secured over $15 million in investment from leading deep-tech investors including Constructor Capital, IP Group and PhotonVentures, alongside government grants, and is scaling rapidly to deploy the fastest optical compute currently available globally.

In analog design, layout isn't an afterthought – it's where matching, parasitics, and noise coupling either preserve a carefully designed circuit's performance or quietly destroy it. As a Senior Analog Layout Engineer at Lumai, you will own the physical implementation of our custom analog and mixed-signal blocks, from data converters to bias and clocking circuits, on advanced CMOS process nodes. You will work in tight feedback loops with circuit designers, translating schematic intent into silicon-accurate layout, and you will be the team's authority on matching techniques, parasitic-sensitive floorplanning, and the physical verification flows that get a design tapeout-ready. You will report to the Senior Analog/Mixed-Signal Design Lead and collaborate daily with analog/mixed-signal circuit designers as well as the broader ASIC physical design team.

Layout and Matching • Own full-custom layout of analog and mixed-signal blocks, including data converters, bias/reference circuits, PLLs, and analog front-end IP • Apply matching techniques appropriate to each block — common-centroid placement, dummy structures, guard rings, and symmetric routing — to preserve circuit-level performance in silicon Parasitics and Physical Verification • Identify and mitigate parasitic-sensitive layout risks, including coupling, IR drop, and substrate noise, working closely with circuit designers on back-annotated simulation • Drive parasitic extraction (PEX) and back-annotated simulation cycles in partnership with circuit designers to close performance margins pre-tapeout • Own DRC, LVS, and ESD/latch-up sign-off for assigned blocks, resolving violations in collaboration with the PDK and foundry liaison team Floorplanning, Mentoring and Post-Silicon • Contribute to floorplanning decisions at the block and sub-system level, balancing area, routing congestion, and noise isolation requirements • Mentor junior layout engineers on matching techniques and advanced-node layout rules as the team grows • Support post-silicon debug by helping correlate layout-dependent effects with bench characterisation findings WHAT WE'RE LOOKING FOR Must-Have • 7+ years of custom analog/mixed-signal layout experience on advanced CMOS process nodes (16nm/12nm class or below) • Deep hands-on expertise in matching techniques (common-centroid, dummy structures, symmetric routing) for precision analog circuits • Strong track record with parasitic-sensitive layout: identifying and mitigating coupling, substrate noise, and IR drop issues • Proficiency with Cadence Virtuoso layout suite and associated DRC/LVS/PEX flows • Experience taking layout from