Analog Layout Intern

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As an Analog Layout Engineer Intern with Marvell, you'll be a member of the Central Engineering business group — the center hub that provides IP to all other business units, including Automotive, Storage, Security, and Networking. You'll be part of a small, high-impact analog layout team working alongside global colleagues in Argentina, Singapore, the U.S., and throughout Europe. Marvell's scale gives you the opportunity to learn broadly across engineering disciplines while also diving deep into the details of analog layout on cutting-edge semiconductor technologies. Here, you'll contribute to real products and real tapeouts — not just simulations. What You Can Expect Translate analog IC schematics into physical layout using Cadence Virtuoso, implementing microelectronic layers that go beyond the schematic level Run design rule checks (DRC), layout versus schematic (LVS), and other physical verification flows to ensure design integrity Collaborate closely with Analog IC Designers to refine, debug, and iterate on layouts until they meet target specifications Participate in regular team meetings and project reviews, presenting progress updates and technical findings to cross-functional global teams Contribute to the development of next-generation semiconductor IP across advanced process nodes (e.g., TSMC N2/N3) What We're Looking For Currently pursuing a Bachelor's in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028 Fundamental understanding of electrical engineering concepts, including analog circuit theory and microelectronics Coursework or hands-on experience in analog design, IC layout, or VLSI design — whether through degree coursework, summer programs, or technical training Familiarity with CAD tools used for physical IC design (e.g., Cadence Virtuoso, Calibre, or similar EDA tools) Strong communication skills with the ability to present technical updates to global teams across different time zones and levels of seniority; fluency in English required Preferred Qualifications: Hands-on experience with physical verification flows including DRC, LVS, ERC, or antenna checks Exposure to advanced process nodes (FinFET, 3nm, 2nm) or analog/mixed-signal layout techniques Experience with scripting languages such as SKILL, Python, or Tcl for layout automation Ability to work independently and manage tasks across multiple concurrent projects with flexibility Expected Base Pay Range (USD) 28 - 56, $ per hour. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. 

 Additional Compensation and Benefit Elements   Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look