MTS – ASIC Device Technology & Silicon Yield Engineering

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Post-Silicon Yield & RMA Leadership Lead end-to-end investigation of silicon yield loss, field returns, customer escalations, and reliability failures. Drive root-cause analysis for complex silicon issues spanning process, design, test, package, and system interactions. Develop hypothesis-driven debug strategies and coordinate multi-functional execution. Own resolution of critical yield and quality issues through containment, corrective actions, and prevention plans. Device Technology & Process Interaction Analysis Analyze device-level failure mechanisms and process sensitivities impacting ASIC functionality and yield. Evaluate design-process interactions affecting analog, mixed-signal, memory, high-speed I/O, and PCIe PHY performance. Partner with foundry teams to understand process variations, excursions, reliability risks, and technology limitations. Translate silicon learning into actionable design and process improvements. Advanced ASIC Design Interaction & Silicon Debug Lead root-cause investigations involving design-process interactions affecting SRAM, PCIe PHY, ONFI interfaces, SerDes, analog/mixed-signal circuits, and high-speed digital subsystems. Analyze silicon failures across transistor, circuit, block, die, package, and system levels. Drive post-silicon debug activities involving design teams, DFT, product engineering, quality, reliability, foundry, and customer support organizations. Debug complex failure mechanisms including: SRAM single-bit and multi-bit failures Read/write margin failures Timing and voltage sensitivity issues PCIe PHY performance degradation Signal integrity and jitter-related failures Yield excursions linked to process variation Field-return and RMA failures Develop silicon characterization plans to isolate process, design, and test-related contributors. Drive silicon learning feedback into next-generation ASIC architecture and design methodologies. Failure Analysis & Physical Debug Drive advanced FA activities including: FIB SEM/TEM EFA OBIRCH LVP Emission microscopy Physical cross-section analysis Correlate failure signatures with design, process, and manufacturing data. Interpret FA results and convert findings into clear engineering actions. multi-functional Technical Leadership Lead technical reviews with Product Engineering, DFT, Design, Reliability, Quality, Operations, Foundry, and external partners. Present complex technical findings to executive leadership. Influence design and technology roadmaps to improve future product robustness and yield learning.

Education Ph.D. or M.S. or equivalent experience in: Electrical Engineering Materials Science Physics Semiconductor Engineering Related technical rigor Experience 12+ years of semiconductor industry experience. Strong background in advanced CMOS technology and silicon product development. Proven success leading yield improvement, RMA, and failure analysis efforts. Experience working directly with foundries and OSAT partners. Technical Expertise Deep understanding of CMOS device physics and advanced semiconductor process technologies. Strong expertise in SRAM architecture, memory design fundamentals, memory margin analysis, and failure mechanisms. Strong understanding of high-speed interface technologies including PCIe, ONFI, LPDDR, SerDes, and clocking architectures. Experience with post-silicon debug and characterization of complex ASIC devices. Expertise in process-design interaction analysis and variation-aware design methodologies. Strong knowledge of: Signal Integrity (SI) Power Integrity (PI) Timing closure methodologies Device variability and mismatch analysis Reliability-induced