Senior SerDes & Analog Layout Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s Intelligent Cloud mission. SCHIE delivers core infrastructure and foundational technologies supporting Azure, Microsoft 365, Teams, Xbox, and next-generation AI platforms at hyperscale, with a focus on high-quality, efficient, and trusted cloud hardware solutions. As Microsoft’s cloud and AI businesses continue to grow, high-speed die-to-die (D2D) connectivity is critical to delivering scalable, power-efficient custom silicon. The Semi & Custom IP team develops advanced analog and mixed-signal IP, including D2D SerDes interfaces, for next-generation AI accelerators, cloud infrastructure, and custom silicon platforms powering Microsoft’s future AI services and datacenter offerings. We are looking for a Senior D2D SerDes & Analog Layout Design Engineer to be a hands-on technical contributor and layout lead for matching-critical analog and D2D SerDes physical implementation. This high-visibility role will own complex subsystem deliverables, guide layout execution and technical reviews, collaborate across design and integration teams, and drive production-ready IP from planning through tapeout. The position offers opportunities to broaden technical scope, deepen D2D and advanced-node expertise, and grow technical leadership through direct work on strategic silicon programs. #SCHIE Responsibilities Drive physical implementation of complex D2D SerDes and analog/mixed-signal IP in advanced process technologies, from floorplanning through tapeout, signoff, and integration. Own or co-own top-level D2D analog front-end floorplanning and integration, including partitioning, hierarchy, die-edge constraints, bump or micro-bump alignment, ESD interfaces, power distribution, sensitive routing, and package-aware implementation tradeoffs. Establish matching and parasitic-control strategies for critical circuits using symmetry, common-centroid placement, interdigitation, device orientation control, dummy structures, shielding, guard rings, isolation, return-path planning, and gradient mitigation. Help lead D2D layout execution across multiple blocks and contributors by defining implementation plans, coordinating technical work, reviewing layouts, resolving cross-block dependencies, and supporting milestone closure. Partner with circuit design leadership to translate electrical requirements into physical implementation constraints and make layout-versus-circuit tradeoffs that improve system-level power, performance, area, signal integrity, reliability, and yield. Identify and resolve layout risks for high-speed transmitter, receiver, clocking, bias, equalization, PLL/DLL, and related analog front-end circuitry. Collaborate across signal integrity, package, ESD, physical design, CAD, foundry, reliability, and SoC teams to align interface definitions and integration requirements for the assigned subsystem. Own physical verification and signoff closure, including DRC, LVS, ERC, antenna, density, extraction review, EMIR, reliability analysis, layout-dependent effects, and complex cross-hierarchy debug. Contribute to layout quality criteria, review checklists, release requirements, and signoff evidence for internally and externally developed D2D and analog IP. Deliver production-ready IP collateral, including GDS/OASIS, LEF abstracts, integration views, interface documentation, waiver rationale, review records, and signoff packages for SoC and package integration. Develop and improve analog layout methodologies, reusable templates, automation flows, and productivity solutions using SKILL, TCL, Python, or similar scripting languages. Provide technical guidance and mentorship through design reviews, coaching, documentation, and sharing of advanced-node analog and D2D layout practices. Coordinate technical execution with contractors, vendors, and geographically