Systems Engineer, Staff - SoC Interconnect / NoC Systems Architecture

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly motivated Systems Engineer to drive the architecture and development of next generation System-on-Chip (SoC) interconnect solutions powering data center, automotive, smartphone, notebook, tablet, XR, smart glasses, and emerging compute platforms. The candidate will be a key member of the NoC Systems Architecture Team , responsible for defining system requirements, developing Network-on-Chip (NoC) architecture specifications, and collaborating across multiple engineering disciplines to deliver scalable, high-performance, and power-efficient SoC solutions.

Interconnect Architecture and System Definition Contribute to the definition and evolution of SoC interconnect and Network-on-Chip (NoC) architectures. Gather and analyze system requirements, understand product use cases, and translate them into interconnect architecture and functional specifications. Define performance, scalability, quality-of-service (QoS), coherency, and latency requirements for interconnect subsystems. Evaluate and recommend suitable NoC topologies, routing algorithms, arbitration mechanisms, and traffic management schemes. System Modeling and Analysis Develop and utilize behavioral or analytical models to study NoC performance and design trade-offs. Analyze system traffic patterns and data flows to optimize interconnect bandwidth, latency, and power efficiency. Collaborate with performance teams to validate architectural decisions through modeling and simulation. SoC Architecture Collaboration Work closely with CPU, GPU, AI/ML, Multimedia, Memory, Security, Power, and other subsystem teams to define interconnect requirements. Develop a strong understanding of: SoC boot flows Security architecture Clock and reset architecture Power management architecture System-level data flows and performance requirements Cross-Functional Engagement Partner with architecture, RTL design, verification, physical design, floorplanning, power, and silicon validation teams throughout the product lifecycle. Collaborate with global engineering teams across multiple sites to ensure alignment on interconnect architecture and implementation. Support post-silicon validation efforts by correlating pre-silicon assumptions with measured silicon behavior. Technology Leadership and Innovation Stay current with evolving industry standards, including: ARM AMBA specifications CHI , AXI, AHB, ACE/ACE-Lite protocols PCI Express (PCIe) CXL Ethernet UALink Coherency and virtualization technologies Low-power design methodologies Drive continuous improvements in interconnect architecture, design methodologies, performance optimization, and power efficiency. Propose innovative architectural solutions for future generation NoC and interconnect technologies.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 7 to 11 years of experience in SoC architecture, SoC design, NoC architecture, or related system engineering roles. Strong understanding of on-chip interconnect concepts and industry-standard protocols, including: ARM CHI AXI/AHB ACE/ACE-Lite NoC architectures and coherency concepts Good understanding of digital design fundamentals and RTL implementation concepts. Hands-on experience with Verilog/SystemVerilog based RTL development and SoC design methodologies. Understanding of multi-core ARMv8/ARMv9 architectures, cache coherency, memory hierarchy, and virtualization concepts. Familiarity with performance analysis, system modeling, and architectural trade-off studies. Strong analytical, problem-solving, communication, and collaboration skills.

Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field. Experience with large-scale SoC architecture for data center, AI/ML, mobile,