Advanced Package Technology, Principal Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact The Marvell Advanced Packaging R&D team is responsible for package design and technology development to meet the electrical, mechanical, thermal and system requirements for the next generation high performance computing (HPC), Artificial Intelligence (AI) and networking solutions. The group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability, involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry-leading packaging technologies. What You Can Expect Develop packaging technology roadmap for AI XPU, XPU-attach and Switch Explore technologies beyond what is currently available, make recommendations, and create and protect IP to maximize performance. Create new package technology concepts from open ended ideas, perform routing feasibility, signal and power integrity studies for design optimization. Explore technology feasibility and create proof-of-concept samples and productize technologies.  Define package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy, and thermal design envelope. Lead co-design efforts across silicon design, floorplanning, PDN modeling, and mechanical/thermal reliability. Lead package material selection, substrate stack-up definition, mechanical modeling, and reliability analysis. Partner with silicon design teams to co-optimize die floorplan, bump map, TSV, and RDL requirements. Work with OSATs / Foundry partners to evaluate process capability, manufacturability, yield, and cost. Drive package qualification and reliability validation to volume readiness.

Experience in advanced package and substrate technologies with deep understanding of process and materials, component and board level reliability, warpage and thermal management. Experience in managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries. Deep knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as design methodology and strategies. Experience in signal and power integrity simulations, analysis and optimization for 2.5D and 3D packages including interface with memory, interposer, substrates and PCBs.  Ability to   determine optimal signal routing, power delivery verification and package size determination Bachelor’s degree or a master’s degree in mechanical engineering, material science or related fields and 8-10 years of related professional experience, or PhD degree / post-doc with 5+ years of experience.  Experience interfacing with product design teams for optimized floor-planning, package related design input and power delivery network design. Skills needed to be successful in this role:   Ability to develop an idea into a proof of concept and then a proof of concept into a productizable technology Deep understanding of fundamental concepts of signal and power integrity, transmission line and