Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building memory interface IP that has to work at the bleeding edge of performance, power, and reliability. Not just meet spec, but hold up under real-world corner cases that no one thought to write down. You know that the difference between a memory controller that ships and one that gets redesigned six months later is usually an architectural decision made early, and you are the kind of architect who sees around those corners. You think in tradeoffs. Bandwidth versus latency. Area versus configurability. What works in simulation versus what survives silicon. When someone asks if we can support a new HBM3 feature, you do not say yes or no, you say here is what it costs and here is what we get, and you have the depth to back it up with real numbers. You have worked across HBM, DDR, LPDDR, or similar high-speed memory protocols long enough to know where the complexity lives. Maybe it is training algorithms. Maybe it is clock domain crossings. Maybe it is how you partition the PHY interface so verification does not become a nightmare. You do not need to be told what matters, you already know. At Synopsys, you will define the architecture for memory IP that powers AI accelerators, data center processors, and mobile SoCs used by millions of people. The team is global, the problems are hard, and what you design will ship.

Define and own the digital architecture for HBM, DDR, or LPDDR memory controllers, from high-level partitioning through RTL implementation strategy Drive design plans for complex memory interface blocks, balancing performance, area, power, and verification complexity across chip and block levels Collaborate with PHY teams, verification engineers, and product architects to ensure seamless integration and protocol compliance Evaluate and select design methodologies, tools, and flows that improve quality, reduce cycle time, and scale across product lines Mentor engineers on architecture decisions, RTL best practices, and debug strategies for high-speed memory interfaces Work directly with customers and internal stakeholders to align on feature requirements, timing constraints, and delivery milestones Review and guide RTL, testbenches, and verification plans to catch architectural issues before they become silicon problems The Impact You Will Have Your architecture decisions will define the performance ceiling and power floor for memory IP used in next-generation AI and data center chips You will reduce time-to-market by building memory controllers that are easier to verify, integrate, and customize across multiple product variants The IP you help design will ship in millions of devices, from smartphones to high-performance computing systems You will elevate the technical depth of the team by mentoring engineers and establishing architectural patterns that scale Your ability to navigate ambiguity and make sound tradeoffs will directly influence which features ship and which get deferred You will help Synopsys maintain its leadership position in memory IP by driving innovations in HBM3, DDR5, LPDDR5X, and beyond The methodologies and design frameworks you put in place will improve quality and productivity across future memory IP projects What You'll Need 12 - 15+ years of hands-on experience in ASIC digital design, with significant time spent on memory interfaces or high-speed IO protocols