Advanced Packaging Intern, MS - Summer 2027
Marvell Technology
- Location
- Santa Clara, CA
- Employment
- Internship
- Work model
- On-Site
- Level
- Intern
- Posted
- Sep 5, 2026
Skills
About this role
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging team is responsible for supporting customers with package designs that meet challenging electrical requirements. High speed signaling and challenging power delivery networks require complex and custom solutions to meet constantly advancing application needs. Many of the new designs require multi-chip and multiple component configurations with high-speed IP requirements. In addition, our team is advancing Marvell's expertise in 3D packaging, Co-packaged optics and cutting-edge substrate materials. We work with the world's leading manufacturers to solve our client's most challenging designs and integrations with industry-leading packaging techniques. What You Can Expect Perform signal integrity (SI), power integrity (PI), and electromagnetic (EM) simulations for advanced packaging and high-speed interconnects. Evaluate package and PCB designs to ensure electrical performance requirements are met. Analyze power distribution networks (PDNs) and high-speed channels to identify and resolve signal and power delivery issues. Execute simulation and verification activities supporting SI/PI sign-off. Collaborate with package design, layout, hardware, and IP teams to optimize electrical performance. Develop scripts and automation tools using Python, MATLAB, or similar tools to improve analysis workflows. Document results and present technical findings to cross-functional engineering teams.
What We're Looking For
The ideal candidate will have an interest in hardware design and experience working on signal and power integrity verification and design optimization. A knowledge of Electrical Engineering concepts, circuit extractions and simulation, as well as design methodology and strategies is required. Currently enrolled in a Master's Degree program studying Electrical Engineering, Computer Engineering, or a related discipline, with an expected graduation date between Fall 2027 – Summer 2028. Strong interest in hardware design and strong understanding of electromagnetic fundamentals, signal integrity concepts and circuit simulation techniques. Knowledge of circuit simulation techniques and experience evaluating electrical behavior of package, PCB, or interconnect structures. Exposure to frequency-domain and time-domain analysis methodologies. Experience with electrical simulation tools for signal integrity, power integrity, or electromagnetic analysis. Ability to organize technical information, analyze data, document results, and communicate findings effectively. Strong collaboration skills and the ability to work with engineers across multiple disciplines, teams, and locations. Interest in hardware design, advanced packaging technologies, and design optimization.
Preferred Qualifications
Experience evaluating package or PCB designs for challenging electrical requirements. Hands-on experience with 2-D/3-D electromagnetic simulation tools such as Ansys HFSS, SIwave, Cadence Clarity, or similar tools. Experience performing signal integrity (SI), power integrity (PI), channel analysis, power distribution network (PDN) analysis, or related simulation activities. Familiarity with advanced packaging technologies, including 2.5D and 3D packaging architectures. Experience collaborating with physical designers, layout engineers, or IP teams to optimize electrical performance. Familiarity with IC package design and layout tools such as