Principal Memory Subsystem Engineer (Design or DV)

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.  As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.   We are looking for a  Principal Memory Subsystem Engineer (Design or DV) to join the team.

Provide technical leadership for Memory Subsystem development as a Design or Design Verification (DV) engineer, driving solutions from architecture and microarchitecture through silicon bring-up. Lead the design, integration, and verification of high-performance, complex SoC subsystems, with a focus on memory technologies, bandwidth, latency, utilization, power, and overall system efficiency. Collaborate closely with Architecture, RTL Design, DV, Physical Design (PD), Design-for-Test (DFT), Firmware, and Post-Silicon teams to resolve system-level issues and deliver robust silicon. Drive vertical and horizontal IP/component reuse across projects and platforms, ensuring scalable and efficient subsystem architectures. Provide technical leadership through mentorship, design reviews, code reviews, and cross-functional collaboration, helping to establish and maintain engineering best practices. Develop and optimize subsystem architectures involving PCIe, HBM, imaging and control subsystems, interconnect fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement. Drive design implementation, including microarchitecture specification, RTL development and integration using Verilog/SystemVerilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, lint, and RDC. Lead verification activities, including development of verification strategies and test plans, UVM-based constrained-random environments, scoreboards, checkers, assertions, functional coverage, and coverage closure. Debug complex design and system-level issues across simulation, emulation, and silicon, working across disciplines to identify root causes and implement effective solutions. Drive execution in an Agile development environment, including sprint planning, feature deployment, code reviews, issue resolution, and continuous improvement of design and verification processes. Champion high-quality engineering execution and contribute to delivering cutting-edge, custom IP and SoC solutions that meet demanding performance, power, efficiency, and schedule requirements.

Required/minimum qualifications Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical