Senior CPU Physical Design Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Partner with RTL, Architecture, DFT, and Technology teams to lead architectural feasibility studies and optimize Power, Performance, and Area (PPA) tradeoffs. Own block- and IP-level physical design from synthesis through Place and Route (PnR), continuously pushing the envelope on PPA improvements and design convergence. Work in a tight loop with cross-functional designers to debug critical timing paths, applying advanced physical design techniques to guide optimal implementation strategies. Extract maximum value from industry-standard EDA tools and develop custom methodologies to ensure state-of-the-art implementation. Execute critical signoff activities including Static Timing Analysis (STA), signoff-based timing/power recovery, and comprehensive electrical/layout checks, while acting as a core pillar of the physical design group to foster seamless collaboration across teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science or a related field, or equivalent practical experience. 8 Years of experience in high-speed design, including implementation and PPA optimization leveraging industry-standard toolsets. Preferred qualifications: Experience applying AI/ML-assisted physical design techniques to drive next-generation scaling and faster physical design closure. Experience in sign-off convergence areas like STA electrical checks, and physical verification. Expertise in physical design, diagnosing complex timing bottlenecks, and implementing advanced, scalable physical solutions. Proficient in scripting (Python, Tcl, Perl) and data mining, extracting design parameters, analyzing QoR metrics, and identifying performance trends. Understanding of EMIR flows and design reliability for high-frequency circuits, with expertise in industry-standard tools. Track record of delivering high-performance silicon across advanced technology process nodes (e.g., 5nm, 3nm, 2nm+).