SoC Verification Senior Engineer in District 7

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles ASIC Verification Senior Engineer IP Verification Senior Engineer Design Verification Senior Engineer SoC Verification Senior Engineer Digital Verification Senior Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in verification knowing that finding the bug before tapeout is the difference between a product that ships and one that doesn't. You understand that a good testbench is not about coverage numbers on a dashboard, it is about building an environment that actually stresses the design in ways that matter. You think in corner cases. When someone describes a new protocol feature, you are already mentally mapping the sequences that will break it. You are comfortable working in System Verilog and UVM, but you also know when to drop into directed tests because constrained random is missing something specific. Debugging does not frustrate you, it energizes you. You will spend hours in waveforms tracing a signal across clock domains because you know that is where the real work happens. Working with RTL designers across time zones does not slow you down. You ask the right questions, align on what needs verification, and move forward even when the spec is still being written. At Synopsys, you will work on IP that powers everything from AI accelerators to autonomous vehicles.

Define block and subsystem verification plans that map directly to design specifications and protocol requirements Build UVM testbenches in System Verilog, including agents, scoreboards, coverage models, and assertion monitors Write constrained random and directed tests that exercise protocol compliance, corner cases, and error injection scenarios Debug RTL and testbench failures using simulators and waveform analysis to root cause and resolve issues Collaborate with RTL designers and global verification engineers to align on design intent and coverage goals Apply formal verification techniques to prove properties and close coverage gaps Drive verification closure by tracking coverage metrics and iterating on test plans until signoff The Impact You Will Have Your verification work determines whether IP blocks integrate cleanly into customer SoCs or require costly respins You will close critical coverage gaps that prevent silicon bugs from reaching production The testbenches you build will be reused across multiple IP releases, multiplying your impact Your collaboration with designers will catch issues early, reducing debug cycles and accelerating tapeout You will help establish verification best practices for a newly formed team in Ho Chi Minh City The IP you verify will enable next generation AI, 5G, HPC, and automotive systems used worldwide What You'll Need Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science 2+ of hands-on design verification experience in the semiconductor industry Strong proficiency in System Verilog and UVM for building testbenches and implementing coverage Working knowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR Experience with industry standard simulators like VCS, Xcelium, or Questa, and version control systems Solid scripting skills in Python, Perl, or Tcl for automation and regression management Who You Are You can take a protocol spec and translate it into a verification plan that covers what matters, not just what is easy to test When a regression fails before a milestone, you dig into the waveform and find the root cause