Senior ASIC Package Design Engineer

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role supports the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will collaborate with internal teams for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

• Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.

• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.

• Establish package design standards, methodologies, and best practices.

• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.

• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.

• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.

• Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network (PDN) design, and decoupling strategy

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