Senior STA Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Senior STA Engineer – Job Description

Position: Senior STA EngineerExperience: 4–8 yearsLocation: AhmedabadEmployment Type: Full-time

We are looking for a Senior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.

• Own STA and timing signoff activities from synthesis through physical design and tape-out.

• Perform MCMM/MMMC timing analysis across all functional and test modes.

• Analyze and debug setup, hold, recovery, removal, min/max, and clock-related violations.

• Develop, review, and validate SDC constraints, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.

• Perform detailed clock tree and clock timing analysis, including skew, latency, uncertainty, jitter, and clock reconvergence.

• Drive timing closure in collaboration with RTL, synthesis, physical design, and ECO teams.

• Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions.

• Perform timing