Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

Descriptions & Requirements

Job Description and Requirements

Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years verifying silicon that ships into data centers, AI accelerators, and high-performance systems where failure is not an option. The protocols you verify, PCIe, CXL, DDR, Ethernet, are not abstract specs to you. They are living, breathing systems with corner cases that only reveal themselves at 3 a.m. during a regression run, and you are the engineer who finds them before tape-out. You think in layers. You can debug a failing assertion in the UVM environment, trace it back to an RTL timing issue, and then connect it to a protocol compliance gap, all without losing the thread of what actually broke. When someone says "coverage is at 95%," you ask which 5% is missing and whether it matters. You do not wait for perfect documentation. Specs are incomplete, architectures evolve, and you have learned to work with what you have, ask the right questions, and build verification environments that adapt as the design matures. You have strong opinions on what makes a testbench reusable versus one that becomes technical debt, and you are not afraid to push back when a verification strategy does not account for real-world integration scenarios. At Synopsys, you will verify Interface IP that powers the semiconductor industry's most critical applications, and the team you work with will expect you to lead, not just execute.

Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality Debug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices The Impact You Will Have Your verification work will directly determine the quality and reliability of IP integrated into AI platforms, cloud infrastructure, and automotive systems used globally The testbenches and verification IP you build will be reused across multiple product generations, multiplying your impact across the organization Your coverage strategies and signoff criteria will set the standard for verification quality across the Interface IP portfolio The protocol bugs you catch pre-silicon will prevent costly respins and delays for customers building next-generation SoCs Your technical leadership will shape verification methodology improvements that raise the bar for the entire engineering team The mentorship you provide will accelerate the growth of engineers who will carry forward the verification practices you help establish Your collaboration with architecture and design teams will influence early design decisions that make verification more efficient and products more robust What You'll Need Bachelor's or Master's in Electrical