ASIC Design Engineer, Sr. Staff-18490

General Information

Job Title

ASIC Design Engineer, Sr. Staff-18490

Job ID

18490

City

US (non-CA) Off-Site

State/Province

US (non-CA) Off-Site Office

Date Posted

26-Aug-2026

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Remote Eligible

Yes

Base Salary Range: $138000 - $ 208000

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years working at the boundary between hardware and software, writing code that must configure real silicon, not just pass a test suite. You know that the difference between a PHY that trains reliably and one that fails intermittently often comes down to a register sequence you wrote three months ago, and you are the kind of engineer who thinks through those sequences before they become customer issues. You are comfortable moving between C firmware that runs on embedded controllers and Python scripts that automate build flows. When a new feature lands from the design team, you do not wait for perfect documentation. You dig into RTL, ask the right questions, and figure out what the configuration software needs to do to make it work in the real world. Debugging is where you thrive. You have traced boot failures through firmware logs, register dumps, and waveform viewers enough times to know what good bring-up looks like and what smells wrong. You do not just fix the symptom; you understand the root cause and make sure it does not come back. At Synopsys, you will work on DDR PHY IP that ships everything from data center servers to automotive SoCs. The team is small, the problems are hard, and what you build directly affects whether our customers' chips work on first silicon.

Design, develop, and maintain PHYINIT, the configuration software that initializes and configures Synopsys DDR PHY IP across multiple product generations Write runtime firmware that runs on embedded controllers within the PHY, managing training sequences, calibration, and operational modes Collaborate directly with digital design and verification engineers to enable new DDR features, translating RTL changes into working configuration code Debug PHY bring-up issues on customer silicon and internal test chips, analyzing register states, firmware logs, and waveforms to isolate root causes Build and improve automation flows using Python or Perl to generate configuration code, validate settings, and streamline integration into customer SoCs Own the software/firmware release process for PHYINIT, ensuring compatibility across design revisions and customer use cases Participate in architecture discussions for future PHY generations, representing the software and firmware perspective early in the design cycle The Impact You Will Have Your configuration software will determine whether DDR PHY IP integrates cleanly into customer designs or creates weeks of bring-up delays The firmware you write will run on millions of chips across data center, mobile, automotive, and AI applications Your debugging work will directly reduce time to first silicon success for customers building next-generation systems The automation flows you build will accelerate how quickly the team can validate new features and release to customers Your input on design decisions will shape how configurable and de-buggable future PHY generations are from day one The quality of your code will affect how reliably high-speed memory interfaces train and operate in production systems Your collaboration with design and verification will close the loop