Manager, ATE Test Engineering

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs is seeking a Manager, ATE Test Engineering to lead our Test engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance products from silicon bring-up through high-volume manufacturing in advanced process nodes.

Astera Labs is looking to build and scale the Test Engineering team responsible for developing scalable ATE solutions for complex mixed-signal silicon products and high-speed products that power next-generation AI infrastructure. You will shape test strategy, guide execution across wafer sort and final test, and ensure products move confidently from design through silicon bring-up and high-volume production.

This is an opportunity to combine technical depth with engineering leadership at a hyper-growth connectivity company. Your decisions will directly influence product quality, manufacturing readiness, and customer experience. You will partner across design, DFT, product engineering, operations, and manufacturing to improve coverage, quality, cost, and test time as Astera Labs scales purpose-built connectivity for rack-scale AI systems.

• Team Leadership & Organization Building

• Build, mentor, and lead a high-performing team of ATE Test engineers owning a diverse portfolio of connectivity products purpose-built for AI infrastructure

• Establish scalable processes, best-known methods (BKMs), and operational excellence frameworks as the organization grows

• Make sound technical and organizational decisions in a fast-paced, dynamic environment with competing priorities

• Test Strategy and Product Ownership

• Define end-to-end ATE test strategies and plans for high-speed connectivity products from design engagement through high-volume production.

• Establish coverage, quality, test-time, cost, and yield objectives, and drive measurable improvements across the product lifecycle.

• Lead silicon and ATE bring-up, bench-to-ATE correlation, production release, and ongoing test optimization.

• ATE Hardware, Software, and Silicon Validation

• Guide to tester platform selection and development of load boards, interface hardware, and test solutions for wafer sort and final test.

• Direct ATE program development, pattern implementation, debug, and resource optimization on Advantest 93k or Teradyne platforms.

• Drive characterization and production test of high-speed SerDes and mixed-signal interfaces, including PCIe, Ethernet, DDR, NVMe,