Photonic Engineer, Senior

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > RFIC Design General Summary: Define, design, and develop photonic integrated circuits for next-generation silicon photonics platforms targeting high-speed   optical interconnect and DWDM transceiver applications. Perform photonic device design covering both active components   and passive components using 3D structure simulation tools and foundry PDKs. Collaborate cross-functionally with other designers, and systems teams in a DWDM transceiver product project.   Utilize script-based workflow with AI to automate simulation, layout generation, and data analysis. Work with testing engineers on post-fabrication device characterization in the lab to validate designs and close the loop between simulation and hardware. Required for This Role:   - Bachelor's degree in EE, Physics, Optics, or related field with 5+ years of PIC design experience, OR   - Master's degree in EE, Physics, Optics, or related field with 3+ years of PIC design experience, OR   - PhD in EE, Physics, Optics, or related field with 1+ year of PIC design experiences.   - 2+ years hands-on with: Lumerical (FDTD, MODE, CHARGE, INTERCONNECT), and any layout editor/viewer (Cadence Virtuoso, KLayout, or  equivalent), and Python.   - Hands-on design experience with silicon-photonics foundry PDKs  - System-level understanding of optical link budgets, DWDM channel plans, OMA/TDECQ, and transceiver power allocation.     Preferred Qualifications:   - 2+ years of Co-Packaged Optics (CPO) design experience — chip-to-chip optical coupling, CPO-specific constraints, or tape-out in a CPO-targeted node.   - 2+ years of PIC-EIC co-design — joint optimization for high-speed transceivers, including driver/TIA co-simulation with active photonic devices.   - System-level photonic simulation tools: VPI Photonics, Lumerical Zemax OpticStudio, or equivalent.   - DWDM wavelength control loops, thermal tuning, closed-loop resonance lock for ring-modulator transmitters.   - Track record of photonic tape-outs (MPW or full-reticle) with post-silicon characterization closure.   - Publication record or patent filings in integrated photonics.     Principal Duties and Responsibilities   - Design active (MRM, MZM, photodetectors) and passive (edge/grating couplers, power splitters, wavelength MUX/DEMUX) photonic devices      from spec through tape-out using foundry PDKs and 3D structure optical simulation.   - Perform 3D photonic simulation (FDTD, MODE, INTERCONNECT, and CHARGE for carrier/electro-optic effects) to validate device      performance and iterate to target specs.   - Develop and maintain script-based workflows — leveraging AI-assisted tooling — to automate parameter sweeps, layout      generation, and measurement-data processing.   - Review and sign off on PIC physical layouts produced by the dedicated layout engineer from physical design team.   - Collaborate with other PIC designers, EIC designers, and package teams to run co-simulations. Align interface specs, and validate electro-optical      performance in the full DWDM transceiver system.   - Execute and interpret post-fabrication characterization lab testing.   - Close the simulation-to-hardware loop by correlating characterization data with models and proposing corrections.   - Participate in cross-functional design reviews spanning component performance, tape-out readiness, and system link budget.   - Maintain internal technical documentation: design specs, simulation methodology, characterization reports, and tape-out checklists.   - Track silicon photonics, CPO, and DWDM transceiver developments, and apply emerging techniques to improve design quality and      time-to-tape-out.     Level of Responsibility   - Works under some supervision, with high independence for component-level design decisions.   - Provides technical guidance and layout-review feedback