Senior Engineer - Low Power Design

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 About this Opportunity Join Ericsson's cutting-edge journey to shape the future of 5G networks! As a Low-Power Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you. At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, innovative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom! We are hiring a Low-Power Physical Design Engineer to own chip-level power estimation, analysis, and signoff using Synopsys PrimePower (PTPX) on high-performance, power-constrained SoC designs at advanced process nodes. You will define and drive power closure methodology, coordinate with RTL, physical design, and architecture teams to meet power budgets, and contribute to synthesis and STA flows as a secondary responsibility. This role is critical to the chip's power-performance story from early RTL through tape-out. What you will do: 
 Dynamic Power Analysis •    Own dynamic power analysis using Synopsys PrimePower (PTPX) across all design modes, workloads, and PVT corners. •    Generate, annotate, and validate switching activity files (SAIF / VCD) from RTL and gate-level simulations for accurate power estimation. •    Define representative workload scenarios and activity vectors for meaningful power measurement across use cases (active, idle, burst). •    Perform clock-domain-level, block-level, and full-chip dynamic power breakdowns; identify high-power contributors and drive optimization. •    Collaborate with RTL designers to implement low-power techniques — clock gating, operand isolation, fine-grained power gating — and verify their effectiveness in PTPX. Static & Leakage Power Analysis •    Perform leakage power analysis across process corners and temperatures; validate multi-Vt cell usage and leakage reduction strategies. •    Analyze static power contribution from individual blocks and guide Vt optimization decisions in partnership with synthesis teams. •    Validate UPF/CPF power intent implementation — isolation cells, level shifters, retention registers — for correctness and power impact. Power Integrity & IR Drop •    Coordinate with physical design and package teams on static and dynamic IR drop analysis using Ansys RedHawk or Synopsys VoltageStorm. •    Analyze electromigration (EM) violations on power and signal nets; provide constraints and guidance to P&R for power grid fixes. •    Define power delivery network (PDN) requirements and validate against IR drop targets throughout the design cycle. •    Cross-correlate PTPX switching activity maps with IR drop hotspots to identify and resolve power integrity risks. Power Signoff & Methodology •    Define and own the power signoff checklist and sign-off criteria; lead power-related tape-out readiness reviews. •    Build and maintain power estimation flows for early-stage RTL power budgeting and architecture trade-off studies. •    Track power metrics across design milestones; produce detailed power reports for program management and architecture teams. •    Develop and document power analysis methodology, scripts, and best practices for reuse across projects and technology nodes. •    Engage with EDA vendors (Synopsys) to evaluate new PTPX features, resolve tool issues, and optimize flow runtime. Synthesis Support •    Assist synthesis team in reviewing QoR results from Design Compiler or Genus with a focus on