VLSI Design Verification Masters Level Intern

VLSI Design Verification Masters Level Intern    This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world’s largest HPC and AI systems. As an intern, you’ll work alongside experienced architects, logic designers, and verification engineers on a switch or NIC ASIC verification project for a future generation of Slingshot. You’ll learn industry-standard SystemVerilog and UVM verification techniques, participate in technical design and debug discussions, and see how our team is applying emerging agentic AI workflows to solve complex engineering problems. We are looking for students interested in careers in design verification, HPC and AI systems, or high-performance interconnects. Ideal candidates will have ASIC or VLSI experience through university coursework, industry experience, or self-study. Experience with agentic AI coding tools and workflows is preferred but not required.

Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers Write constrained-random tests Develop and analyze functional coverage to identify verification gaps Debug regression failures and help identify, log, and resolve logic bugs Work directly with ASIC designers and architects Use scripting, automation, and AI-assisted tools to improve the verification process Requirements Pursuing a  M aster’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field Coursework in digital design and computer architecture Experience with object-oriented programming Strong analytical and problem-solving skills Clear written and verbal communication skills Willingness to ask questions, explain your reasoning, and participate in technical discussions Preferred skills Experience with a hardware description language such as Verilog, SystemVerilog, or VHDL Experience with Python, Perl, Tcl, or another scripting language Experience working in Linux development environments Academic, research, or personal projects involving digital hardware Experience working as part of a distributed team Accessibility HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here . Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability. What We Can Offer You: Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing. Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division. Unconditional Inclusion We are