Staff Digital Verification Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building verification environments that have to catch the bugs no one else saw coming, the corner cases that only show up when three protocols collide and a timing edge goes the wrong way. You know that a test plan is only as good as the bugs it finds, and you have learned to think like the design, like the system integrator, and like the customer all at once. You are the engineer who sees a coverage hole at 95% and knows exactly which scenario is missing. Writing assertions is not a checkbox exercise for you, it is how you encode your understanding of what should never happen. You have debugged enough waveforms to know when something smells wrong three layers deeper than the symptom. Leading a verification effort means more than running regressions. You set the strategy, you review the test plans your team writes, and you make the call on what gets verified to what depth. You work directly with RTL designers and architects, not to rubber-stamp their work but to push back when the intent is unclear or the interface is going to be painful to verify. At Synopsys, you will work on DesignWare IP that ships into real products. The verification environments you build will be used across product generations, and the bugs you catch will never make it to silicon.

Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations and configurations Define comprehensive test plans that cover corner cases, protocol compliance, and system-level interactions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable Write and debug complex testbenches, checkers, and assertions that catch real bugs in critical PHY blocks and interface logic Develop software requirements for the PHY that scale across various configurations and use cases Own verification closure for multiple critical blocks within DDR PHYs, including functional coverage, code coverage, and formal signoff Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and surface issues early in the design cycle Manage regression infrastructure and work with the infra team to optimize verification cycles, debug failures, and keep the environment reliable The Impact You Will Have Your verification environments will catch critical bugs before tapeout, directly affecting the quality and time-to-market of DesignWare IP used across the semiconductor industry The test plans you define and review will set the verification standard for the team, ensuring consistent coverage and reducing escapes Your coverage-driven approach will surface gaps that others miss, leading to more robust IP and fewer silicon respins The assertions and checkers you write will become reusable verification IP, accelerating future projects and raising the quality bar Your collaboration with RTL and architecture teams will shape design decisions early, making designs easier to verify and more reliable in the field The regression strategies you implement will directly improve team productivity and reduce verification cycle time Your ownership of critical PHY blocks will ensure that high-stakes features meet functional and performance requirements on schedule What You'll Need Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 4+ years of hands-on