SoC Design Verification Engineer (Up to Principal Level)

Company: Qualcomm Vietnam Company Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The SoC Design Verification organization is seeking engineers to contribute to the verification of complex SoC, subsystem, and IP designs. This role focuses on verification planning, testbench and test development, simulation, coverage closure, debug, and pre-silicon release readiness. The successful candidate will work with architects, RTL designers, integration and synthesis, physical design, firmware, emulation, and post-silicon teams across the global engineering organization.

Translate product, architecture, and block specifications into verification plans, test scenarios, functional coverage, and signoff criteria. Develop and maintain SystemVerilog/UVM testbenches, sequences, drivers, monitors, scoreboards, reference models, assertions, checkers, and reusable verification components. Create directed, constrained-random, assertion-based, and coverage-driven tests for functional, corner-case, error, reset, power-state, security, performance, and low-power behavior. Verify RTL integration, interfaces, register programming, interrupts, clocks, resets, power-management behavior, interconnect, coherency, and subsystem connectivity. Run and debug simulation, regression, lint, CDC, RDC, formal, emulation, FPGA, and gate-level verification flows as applicable. Analyze failures and perform root-cause debug across RTL, testbench, configuration, generated collateral, tools, and environments. Define, track, and close functional, code, assertion, toggle, and coverage metrics; identify verification gaps and improve stimulus quality. Collaborate with RTL, architecture, integration, and synthesis teams to review specifications, identify design issues early, and drive defect resolution. Support emulation readiness, firmware bring-up, SoC integration testing, pre-silicon release, and post-silicon debug preparation. Develop scripts and automation using Python, Perl, Tcl, Shell, or similar languages to improve regression, debug, reporting, and verification productivity. Document verification plans, test results, coverage status, known limitations, waivers, and release recommendations. Level-Specific Expectations A. Engineer Execute defined DV tasks for IPs and subsystems under technical guidance. Develop tests, checkers, coverage models, and regression content; debug routine failures. Support block and subsystem verification, documentation, and coverage closure. B. Senior Engineer Own verification of one or more blocks or features from planning through coverage closure. Independently develop reusable UVM components and lead complex debug. Coordinate issue resolution with RTL, architecture, and DV teams and mentor engineers. C. Staff/Senior Staff Engineer Lead verification of major subsystems or SoC features across multiple teams. Define verification methodology, automation, coverage, regression, and signoff approaches. Drive technical risk identification, cross-functional debug, and delivery against program milestones. D. Principal Engineer Provide technical leadership and set verification strategy for major SoC programs or domains. Resolve complex architectural, verification, performance, and quality issues. Establish scalable methodologies, influence cross-site execution, and mentor senior technical contributors.

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 3+ years of relevant work experience in ASIC, SoC, IP, FPGA, or hardware design verification. Hands-on experience with SystemVerilog and verification environments such as UVM. Experience with simulation, regression execution, waveform debug, and functional coverage analysis. Understanding of digital design fundamentals, RTL, finite-state machines, protocols, clock/reset behavior, and SoC architecture. Experience with scripting or automation using Python,