Quantum Design Enablement Engineer

IonQ, Inc. [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance.

Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before.

We are seeking a Quantum Design Enablement Engineer to join our Manufacturing team in our mission to build the world’s best quantum computers. In this role, you will serve as the primary technical interface between internal quantum chip designers and external foundry partners, playing a key role in bringing next-generation trapped-ion hardware to life.

You will ensure our quantum chip designs transition seamlessly into reliable, scalable fabrication. Core responsibilities include managing the tapeout flow, executing physical verification, performing hands-on layout for test structures and reticle assembly, and partnering with foundries to refine our Process Design Kit (PDK).

• Foundry Interface & PDK Management: Serve as the primary technical point of contact with external foundry partners. Work collaboratively to define, implement, and troubleshoot the PDK, ensuring it accurately reflects foundry capabilities and constraints.

• Tapeout & Mask Validation: Own the tapeout