R&D Engineering, Manager - 18136

Descriptions & Requirements

Job Description and Requirements

Alternate Job Titles Memory Design Engineering Manager Embedded Memory Design Manager SRAM Design Manager Custom Circuit Design Manager We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent a decade in memory design, where the difference between a working SRAM and one that fails at corner cases comes down to understanding transistor-level physics at 5nm. Embedded memory is not just another block, it is what makes or breaks power, performance, and area targets for the entire SoC. You have designed memories that are taped out, went into production, and shipped in real products. Managing a team does not mean you stopped being an engineer. You still review schematics, catch timing issues in sense amplifiers, and push back when specs ignore real silicon behavior. The hardest part of leading design is keeping five engineers aligned on architecture decisions made two months ago, especially when process technology shifts. You are comfortable arguing with system architects about access time versus leakage tradeoffs, then translating that into concrete tasks for your team. You do not wait for perfect specs. You model it in VerilogA, run the numbers, and move. At Synopsys, you will lead memory design work that ends up in chips powering AI accelerators to automotive systems.

Lead architecture, circuit design, and physical implementation of embedded memory IP including SRAM, register files, TCAM, and ROM across advanced nodes Define block specifications with system architects, translating customer requirements into concrete design targets Manage circuit and layout engineers, assign work packages, track progress, and coordinate with project management Execute design and layout reviews, create documentation including datasheets and design reports Model and simulate memory blocks using VerilogA and SystemVerilog to validate architecture before tapeout Support silicon evaluation, analyze field issues, and drive root cause analysis when designs fail Drive continuous improvement in design methodologies and technology evaluation with global teams The Impact You Will Have Deliver memory IP meeting aggressive power, performance, and area targets for AI, automotive, mobile, and data center SoCs Enable faster customer time-to-market with robust, variation-aware memory solutions that work across process corners Build and mentor engineers who can independently own complex memory design challenges Influence memory architecture direction across Synopsys IP portfolio through technical reviews Reduce design risk and silicon respins by catching issues early through rigorous modeling and simulation Expand Synopsys memory IP capabilities into next-generation process nodes Strengthen the technical depth of the Da Nang Design Center through targeted mentorship, knowledge sharing, and continuous process improvement initiatives.

Bachelor's or Master's in Electrical Engineering, Computer Science, or equivalent 10+ years in full embedded memory design flow: architecture, circuit design, physical implementation, compiler automation, characterization, timing, and model generation Deep expertise in SRAM, register file, TCAM, and ROM architecture with advanced custom circuit implementations Direct experience designing memory IP in advanced nodes (7nm, 5nm, or beyond) with variation-aware design understanding Strong knowledge of digital design, verification methodologies, ASIC design flow , and industry-standard EDA tools Experience managing engineering teams including task