ASIC Digital Design, Sr Staff Engineer

Descriptions & Requirements

Job Description and Requirements

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent over a decade building digital designs that ship in real products, not just pass verification. The kind of work where a timing closure mistake or a protocol misinterpretation costs months, and you have learned to catch those issues before they become problems. You think in micro-architectures, not just RTL. When you read a functional spec, you see the tradeoffs between area, power, and performance before you write a single line of SystemVerilog. Die-to-die communication protocols like UCIe, PCIe, or DDR are not buzzwords to you. They are systems you have implemented, debugged at 2am, and optimized until they met both the spec and the silicon constraints. You know the difference between a design that works in simulation and one that closes timing at 28nm with real P&R constraints. Leading a team does not mean delegating tasks. It means sitting with a junior engineer to debug a CDC violation, pushing back when a customer requirement does not make technical sense, and making sure your team understands why a decision was made, not just what to code. You are comfortable working across Noida, Bangalore, and San Jose time zones without losing context or momentum. At Synopsys, you will architect IP cores that power the next wave of automotive and consumer chips, and the designs you own will matter.

Architect and implement RTL designs for high-performance IP cores focused on die-to-die communication protocols including UCIe, targeting consumer and automotive applications Write micro-architecture documents that translate functional specifications into implementable design solutions for complex digital components, defining data paths, control logic, and interface behavior Own the full design flow from RTL coding in SystemVerilog through synthesis, CDC analysis, formal verification, and static timing closure using tools like Fusion Compiler Collaborate directly with the verification team to define testplans, close coverage gaps, and debug corner cases that surface during regression or customer testing Interface with customers to clarify specification ambiguities, align on design intent, and ensure the IP meets real-world integration requirements Mentor a distributed team of ASIC designers across multiple sites, reviewing code, guiding architecture decisions, and building technical depth in protocols and design methodology Drive quality processes including revision control with Perforce, scripting automation in Perl or Shell, and adherence to IP design standards for reuse and scalability The Impact You Will Have Deliver production-ready IP cores that enable high-speed, low-latency die-to-die communication in next-generation automotive and consumer SoCs shipping to millions of devices Define architectural approaches for UCIe and related protocols that position Synopsys as a technical leader in chiplet and multi-die integration markets Reduce customer integration risk and time-to-market by delivering IP that meets timing, power, and area targets out of the box with minimal rework Elevate team capability across Noida and global sites by mentoring engineers on advanced RTL techniques, synthesis strategies, and protocol implementation best practices Influence product roadmaps and feature prioritization by providing technical feedback grounded in real silicon constraints and customer deployment scenarios Strengthen Synopsys IP quality reputation through rigorous design practices, comprehensive documentation, and