SOC Limits Management Architect

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a SoC Limits Management Architect on the HW power team, you will be responsible for defining how our next-generation systems balancing high performance against physical, electrical and thermal constraints. You will bridge the gap between hardware IP, system software, and product requirements to design a holistic Limits Management architecture solution.  In this role, you will work with architects, designers and SW teams to conceive of the architecture and micro-architecture and help with product definition through early involvement in the product life cycle. Your work ensures our SoCs deliver maximum performance under peak current, power and thermal constraints, while maintaining long-term reliability and stability. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health. Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks. Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends. Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies. Drive organizational consensus on feature return on investment (ROI) and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 15 years of industry experience in Power Management or Low-Power Design/Methodology. Experience navigating the full product delivery cycle, from initial architecture definition through to post-silicon productization. Experience with low-power architectures and advanced power optimization techniques.

MS or PhD in Electronics or Computer Engineering, or equivalent, with a focus on computer architecture and power/performance analysis. Experience in peak power management, power budgeting, in-rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management and thermal management and AI. Exceptional leadership and influencing skills, with an ability to influence cross-functional roadmaps and drive ROI-based technical decisions. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail  disability-accomodations@qualcomm.com  or call Qualcomm's toll-free number found  here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies :   Our