ASIC Digital Design, Sr Staff Engineer-18732

Descriptions & Requirements

Job Description and Requirements

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and System Verilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams—architecture, verification, physical implementation, and firmware—to deliver industry-leading SERDES PHY IP solutions. Your leadership style is empowering, fostering growth and development within your team, and you’re committed to cultivating a culture of technical excellence, accountability, and innovation. You bring strategic thinking to every challenge, balancing performance, timing, and powers target while adapting to evolving customer needs. Excellent communication skills and a self-driven attitude make you a trusted mentor and partner, both internally and with customers integrating cutting-edge IP into their SoCs. If you’re excited to shape the future of high-bandwidth, low-latency silicon IP, Synopsys is the place for you. What You’ll Be Doing: Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products. Planning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support. Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles. Mentoring and developing team members, fostering technical growth, and a culture of innovation. Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges. The Impact You Will Have: Delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency. Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications. Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market. Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance. Enhancing product quality and reliability through rigorous design and verification processes/Flows. Facilitating successful customer adoption and satisfaction through expert support and problem-solving. What You’ll Need: Bachelor’s degree or higher in Electrical Engineering, with 8+ years of complex technical development experience. Proficiency in modeling, synthesizable Verilog and System Verilog design concepts and implementation. Strong background in front-end design flows: Linting, synthesis, static timing analysis (STA),CDC/RDC, DFT, and power optimization. Excellent communication skills and the ability to work independently and collaboratively. Understanding the PCIe and Ethernet standard is a plus.

Self-starter independent leader who thrives in a fast-paced, innovative setting and can drive task still closure. Strong problem-solver with a strategic, analytical mindset. Inspirational leader who motivates and develops technical talent. Collaborative team players who excels in cross-functional environments. Effective communicator who can translate complex technical